US-20260130288-A1 - MEMORY PACKAGES AND METHODS OF FORMING SAME

US20260130288A1US 20260130288 A1US20260130288 A1US 20260130288A1US-20260130288-A1

Abstract

A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

Inventors

Chen-Hua Yu
Chung-Hao Tsai
Chuei-Tang Wang
Yih Wang

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20260102

Claims (20)

1 . A package comprising: a memory stack attached to a logic device, the memory stack comprising: a first redistribution structure; a first memory structure over and electrically connected to the first redistribution structure; a second redistribution structure over the first memory structure; and a plurality of first metal pillars on the first redistribution structure and adjacent the first memory structure, the plurality of first metal pillars electrically connecting the first redistribution structure and the second redistribution structure; wherein the first memory structure comprises: a memory die comprising first contact pads; a peripheral circuitry die comprising second contact pads, wherein the memory die is separate from and distinct from the peripheral circuitry die, wherein the first contact pads of the memory die are bonded directly to the second contact pads of the peripheral circuitry die, wherein the peripheral circuitry die is configured for controlling and accessing the memory die; and a plurality of second metal pillars adjacent the memory die, wherein the plurality of second metal pillars is between the first redistribution structure and the peripheral circuitry die, the plurality of second metal pillars electrically coupling the first redistribution structure to the peripheral circuitry die.
2 . The package of claim 1 , wherein the peripheral circuitry die has a lateral dimension that is larger than a lateral dimension of the memory die in a cross-sectional view.
3 . The package of claim 2 , wherein the peripheral circuitry die completely covers an upper surface of the memory die in the cross-sectional view.
4 . The package of claim 1 , wherein the memory die comprises a through via extending through a substrate of the memory die, wherein the through via is electrically coupled to the peripheral circuitry die.
5 . The package of claim 1 , further comprising: a first encapsulant along sidewalls of the memory die and between the first redistribution structure and the peripheral circuitry die.
6 . The package of claim 5 , further comprising: a second encapsulant between the first redistribution structure and the second redistribution structure.
7 . The package of claim 6 , wherein the second encapsulant directly contacts the first encapsulant.
8 . The package of claim 5 , wherein a surface of the first encapsulant is level with a surface of the memory die.
9 . A package comprising: a logic device; a memory stack attached to the logic device, wherein the memory stack comprises: a first redistribution structure, a first side of the first redistribution structure coupled to the logic device; one or more first memory structures coupled to a second side of the first redistribution structure, wherein each of the one or more first memory structures comprises a first memory die, a first peripheral circuitry die directly coupled to the first memory die, and a first encapsulant along sidewalls of the first memory die, wherein the first encapsulant extends between the first redistribution structure and the first peripheral circuitry die; a second encapsulant over the first redistribution structure and along sidewalls of the one or more first memory structures; a second redistribution structure over the second encapsulant; and a first conductive pillar in the second encapsulant, the first conductive pillar electrically coupling the first redistribution structure and the second redistribution structure.
10 . The package of claim 9 , wherein the second encapsulant contacts the first peripheral circuitry die.
11 . The package of claim 9 , further comprising: a second conductive pillar in the first encapsulant adjacent the first memory die.
12 . The package of claim 9 , further comprising: an adhesive layer between the first peripheral circuitry die and the second redistribution structure.
13 . The package of claim 12 , wherein the second encapsulant extends along sidewalls of the adhesive layer.
14 . The package of claim 9 , further comprising: an underfill between the logic device and the memory stack.
15 . The package of claim 14 , wherein the underfill extends along sidewalls of the first redistribution structure.
16 . A package comprising: a logic die; a first redistribution structure bonded to the logic die; a first set of memory structures on and electrically coupled to the first redistribution structure, wherein each memory structure of the first set of memory structures comprises a first peripheral circuitry die, a first memory die and a first encapsulant extending along sidewalls of the first memory die, wherein the first peripheral circuitry die controls the first memory die; a second encapsulant on the first redistribution structure, the second encapsulant extending along sidewalls of the first peripheral circuitry die and the first encapsulant of the first set of memory structures; a first through via extending through the second encapsulant; a second redistribution structure, the first through via electrically coupling a first conductive feature of the first redistribution structure to a second conductive feature of the second redistribution structure, wherein the first set of memory structures is between the first redistribution structure and the second redistribution structure; a second set of memory structures on and electrically coupled to the second redistribution structure; and a third encapsulant on the second redistribution structure, the third encapsulant extending along sidewalls of the second set of memory structures, wherein the second redistribution structure is between the second encapsulant and the third encapsulant.
17 . The package of claim 16 , wherein a bottom surface of the first memory die is level with a bottom surface of the second encapsulant.
18 . The package of claim 16 , further comprising: an adhesive layer between the first peripheral circuitry die and the second redistribution structure.
19 . The package of claim 16 , wherein the first memory die includes a through via electrically coupling the first redistribution structure to the first peripheral circuitry die.
20 . The package of claim 16 , wherein the first peripheral circuitry die and the first encapsulant are laterally coterminous.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation of U.S. patent application Ser. No. 18/526,016, filed on Dec. 1, 2023, which is a continuation of U.S. patent application Ser. No. 17/655,602 , filed on Mar. 21, 2022, now U.S. Pat. No. 11,855,046, issued on Dec. 26, 2023, which is a divisional of U.S. patent application Ser. No. 16/745,718, filed on Jan. 17, 2020, now U.S. Pat. No. 11,282,816, issued on Mar. 22, 2022, which application is hereby incorporated herein by reference. BACKGROUND A High-Performance Computing (HPC) system often includes a High-Bandwidth-Memory (HBM) stack bonded to a logic die. A HBM stack typically includes a plurality of memory dies stacked together, with higher memory dies bonded to the lower memory dies through solder bonding or metal direct bonding through micro bumps. Through-Silicon Vias (TSVs) are formed in the memory dies, so that upper dies may be electrically connected to the logic die through the TSVs. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of a peripheral device of a memory structure, in accordance with some embodiments. FIGS. 2A and 2B illustrates a cross-sectional view of a memory device of a memory structure, in accordance with some embodiments. FIGS. 3A through 3F illustrate the cross-sectional views of intermediate stages in the formation of a memory structure, in accordance with some embodiments. FIGS. 4A through 4H are cross-sectional views of intermediate steps during a process for forming a memory stack, in accordance with some embodiments. FIGS. 5A through 5E are cross-sectional views of intermediate steps during a process for forming a memory package, in accordance with some embodiments. FIGS. 6 through 9 illustrate the cross-sectional views of memory packages, in accordance with some embodiments. FIGS. 10A through 10D are cross-sectional views of intermediate steps during a process for forming a memory package, in accordance with some embodiments. FIGS. 11A and 11B illustrate package structures incorporating memory packages, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Memory packages including a stack of memory structures and methods of forming the same are provided in accordance with various embodiments. The intermediate stages in the formation of the memory stack are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In accordance with some embodiments of the present disclosure, a memory structure includes a memory device (e.g., a memory die) that is bonded to a peripheral device (e.g., another die). The memory device may be hybrid-bonded to the peripheral device, for example. By bonding the peripheral device to the memory device, the distances of the electrical routing between the peripheral device and the memory device may be reduced, which can reduce latency and improve operation speed. Additionally, t