US-20260130290-A1 - PACKAGE STRUCTURE CONTAINING CHIP STRUCTURE WITH INCLINED SIDEWALLS

Abstract

A package structure is provided. The package structure includes a chip structure having a first side region, a second side region, and a corner region. The chip structure has an inclined sidewall, and the first side region and the second side region meet at the corner region. In a top view, the corner region has a rounded profile, the first side region has a first substantially straight-line profile and extends towards the corner region along a first direction. The second side region has a second substantially straight-line profile and extends towards the corner region along a second direction. The second direction is substantially perpendicular to the first direction. The package structure also includes a protective layer laterally surrounding the chip structure.

Inventors

• Shu-Shen Yeh
• Po-Chen LAI
• Che-Chia Yang
• Li-Ling Liao
• Po-Yao Lin
• Shin-puu Jeng

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20260106

Claims (20)

1. 1 . A package structure, comprising: a chip structure having a first side region, a second side region, and a corner region, wherein the chip structure has an inclined sidewall, the first side region and the second side region meet at the corner region, wherein in a top view, the corner region has a rounded profile, the first side region has a first substantially straight-line profile and extends towards the corner region along a first direction, the second side region has a second substantially straight-line profile and extends towards the corner region along a second direction, and the second direction is substantially perpendicular to the first direction; and a protective layer laterally surrounding the chip structure.
2. 2 . The package structure as claimed in claim 1 , further comprising: a second chip structure below the chip structure, wherein the second chip structure extends across an edge of the chip structure.
3. 3 . The package structure as claimed in claim 2 , wherein the second chip structure has a second inclined sidewall.
4. 4 . The package structure as claimed in claim 2 , further comprising: a third chip structure laterally spaced apart from the chip structure, wherein the protective layer laterally surrounds the third chip structure.
5. 5 . The package structure as claimed in claim 4 , wherein the third chip structure has a third inclined sidewall.
6. 6 . The package structure as claimed in claim 5 , wherein the third inclined sidewall is steeper than the third inclined sidewall.
7. 7 . The package structure as claimed in claim 4 , further comprising: a redistribution structure between the chip structure and the second chip structure, wherein the redistribution structure extends across opposite edges of the chip structure, the second chip structure, and the third chip structure.
8. 8 . The package structure as claimed in claim 7 , wherein conductive features of the redistribution structure comprise a plurality of conductive vias, and each of the conductive vias shrinks along a direction towards the chip structure.
9. 9 . The package structure as claimed in claim 7 , wherein a first interface between the chip structure and an insulating layer of the redistribution structure meets a second interface between the chip structure and a conductive feature of the redistribution structure.
10. 10 . The package structure as claimed in claim 7 , wherein a sidewall of the protective layer meets a sidewall of the redistribution structure.
11. 11 . A package structure, comprising: a chip structure over a redistribution structure, wherein the chip structure has an inclined sidewall, the chip structure has a first side region, a second side region, and a corner region, the first side region and the second side region meet at the corner region,, wherein in a top view, the corner region has a rounded profile, the first side region has a first substantially straight-line profile and extends towards the corner region along a first direction, the second side region has a second substantially straight-line profile and extends towards the corner region along a second direction, and the second direction is substantially perpendicular to the first direction; and a protective layer over the redistribution structure, wherein the protective layer surrounds the chip structure.
12. 12 . The package structure as claimed in claim 11 , wherein the chip structure has a first inclined sidewall in the first side region, the chip structure has a second inclined sidewall in the corner region, and the first inclined sidewall is steeper than the second inclined sidewall.
13. 13 . The package structure as claimed in claim 11 , wherein in the top view, the chip structure has a second corner region, a third corner region, and a fourth corner region, and the second corner region, the third corner region, and the fourth corner region have rounded profiles.
14. 14 . The package structure as claimed in claim 11 , further comprising: a redistribution structure having a plurality of insulating layer and a plurality of conductive features, wherein the chip structure is bonded to the redistribution structure, and a first interface between a topmost insulating layer of the insulating layers and the protective layer meets a second interface between the topmost insulating layer and the chip structure.
15. 15 . The package structure as claimed in claim 11 , wherein the protective layer is in direct contact with the inclined sidewall of the chip structure.
16. 16 . A package structure, comprising: a chip structure bonded to a redistribution structure, wherein the chip structure has a first side region, a second side region, and a corner region, the first side region and the second side region meet at the corner region, wherein in a top view, the corner region has a curved profile, the first side region has a first substantially straight-line profile and extends towards the corner region along a first direction, the second side region has a second substantially straight-line profile and extends towards the corner region along a second direction, and the second direction is substantially perpendicular to the first direction; and a protective layer over the redistribution structure, wherein the protective layer surrounds the chip structure.
17. 17 . The package structure as claimed in claim 16 , wherein the redistribution structure has a plurality of conductive features and a plurality of insulating layers surrounding the conductive features.
18. 18 . The package structure as claimed in claim 17 , wherein a first interface between the chip structure and a topmost insulating layer of the insulating layers connects a second interface between the protective layer and the topmost insulating layer.
19. 19 . The package structure as claimed in claim 16 , further comprising: a second chip structure bonded to the redistribution structure and laterally spaced apart from the chip structure.
20. 20 . The package structure as claimed in claim 19 , further comprising: a third chip structure bonded to the redistribution structure, wherein the redistribution structure is between the third chip structure and the second chip structure, and the third chip structure extends across an edge of the second chip structure facing the chip structure.

Description

This Application is a Continuation of U.S. application Ser. No. 18/624,686, filed on Apr. 2, 2024, which is a Divisional of U.S. application Ser. No. 17/459,314, filed on Aug. 27, 2021, the entirety of which are incorporated by reference herein. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuing advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and/or higher degrees of integration. Functional density (i.e., the number of interconnected devices per chip area) has generally increased while feature sizes (i.e., the smallest component that can be created using a fabrication process) have decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. A chip package not only provides protection for semiconductor devices from environmental contaminants, but also provides a connection interface for the semiconductor devices packaged therein. Smaller package structures, which take up less space or are lower in height, have been developed to package the semiconductor devices. New packaging technologies have been developed to further improve the density and functionality. These relatively new types of packaging technologies for semiconductor dies face manufacturing challenges. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A-1F are cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. FIGS. 2A-2D are cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. FIGS. 3A-3D are cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. FIGS. 4A-4F are cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. FIG. 5 is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. FIGS. 6A-6E are cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. FIG. 7 is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. FIGS. 8A-8K are cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. FIG. 9 is a top view of a chip structure, in accordance with some embodiments. FIG. 10 is a top view of a chip structure, in accordance with some embodiments. FIG. 11 is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. FIG. 12 is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. FIGS. 13A-13B are cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. FIGS. 14A-14C are cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depict