US-20260130292-A1 - INTEGRATED CIRCUIT (IC) PACKAGE HAVING A PACKAGE INTERCONNECT INCLUDING A PILLAR AND A SOLDER CAP COUPLED TO A BOTTOM SURFACE OF THE PILLAR TO REDUCE THE HEIGHT OF THE IC PACKAGE

Abstract

An electronic device including an IC having a package interconnect including a pillar and a solder cap coupled to a bottom surface of the pillar to reduce the height of the IC package. The IC package includes a substrate comprising an outer metallization layer having a metal pad and a package mold layer adjacent to the outer metallization layer. The pillar has a top surface and a bottom surface. The pillar extends through the package mold layer with the top surface coupled to the metal pad and the bottom surface coupled to the solder cap. In contrast to conventional package interconnects, such as ball grid arrays (BGA), for example, deploying the solder cap on the bottom surface of the pillar advantageously results in using less solder and tighter pitch between adjacent package interconnects because the width of the pillar is less than a solder ball in a BGA.

Inventors

• Kyudong KANG
• Heun Gun SHIN
• Choi Myungryul
• YongSuk Lee

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260507

Application Date

20241104

Claims (17)

1. 1 . An electronic device, comprising: an integrated circuit (IC) package, comprising: a substrate extending in a first direction, the substrate comprising an outer metallization layer having a metal pad; a package mold layer adjacent to the outer metallization layer; a package interconnect, comprising: a pillar extending in a second direction through the package mold layer, the pillar having a top surface and a bottom surface, the top surface coupled to the metal pad; and a solder cap coupled to the bottom surface.
2. 2 . The electronic device of claim 1 , wherein the package interconnect has a sidewall not comprising a diffusion barrier.
3. 3 . The electronic device of claim 1 , wherein the package mold layer has a second bottom surface, wherein the solder cap extends beyond the second bottom surface by less than or equal to 10 micrometers (μm).
4. 4 . The electronic device of claim 1 , further comprising: a second pillar adjacent to the pillar, wherein a pitch between the second pillar and the pillar is less than or equal to 280 micrometers (μm).
5. 5 . The electronic device of claim 1 , further comprising: a printed circuit board coupled to the solder cap.
6. 6 . The electronic device of claim 1 , further comprising: a solder mask layer between the package mold layer and the outer metallization layer, the pillar extending through the solder mask layer and the package mold layer, the pillar having a width which is the same through both the package mold layer and the solder mask layer.
7. 7 . The electronic device of claim 6 , wherein the width of the pillar is around 150 μm.
8. 8 . The electronic device of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics systems; and a multicopter.
9. 9 . A method of fabricating an electronic device, comprising: forming an integrated circuit (IC) package, comprising: forming a substrate extending in a first direction, the substrate comprising an outer metallization layer having a metal pad; forming a package mold layer adjacent to the outer metallization layer; and forming a package interconnect, comprising: forming a pillar extending in a second direction through the package mold layer, the pillar having a top surface and a bottom surface, the top surface coupled to the metal pad; and forming a solder cap coupled to the bottom surface.
10. 10 . The method of claim 9 , wherein the package interconnect has a sidewall not comprising a diffusion barrier.
11. 11 . The method of claim 9 , wherein the package mold layer has a second bottom surface, wherein the solder cap extends beyond the second bottom surface by less than or equal to 10 micrometers (μm).
12. 12 . The method of claim 9 , further comprising: forming a second pillar adjacent to the pillar, wherein a pitch between the second pillar and the pillar is less than or equal to 280 nanometers (nm).
13. 13 . The method of claim 9 , further comprising: forming a printed circuit board coupled to the solder cap.
14. 14 . The method of claim 9 , further comprising: forming a solder mask layer between the package mold layer and the outer metallization layer, the pillar extending through the solder mask layer and the package mold layer, the pillar having a width which is the same through both the package mold layer and the solder mask layer.
15. 15 . The method of claim 14 , wherein the width of the pillar is 150 μm.
16. 16 . The method of claim 9 , wherein forming the solder cap coupled to the bottom surface comprises: etching into the bottom surface; and electrolytically plating solder to the bottom surface.
17. 17 . The method of claim 16 , wherein forming the solder cap coupled to the bottom surface further comprises: reflowing solder to form the solder cap.

Description

TECHNICAL FIELD The field of the disclosure relates to integrated circuit (IC) packages, and more particularly to design and manufacturing of package interconnects. BACKGROUND Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in an IC package, also called a “semiconductor package” or “chip package.” The IC package includes one or more semiconductor dice (“dies” or “dice”) as an IC(s) that are mounted on and electrically coupled to a package substrate to provide physical support and an electrical interface to the die(s). The die(s) is electrically interfaced to metal interconnects (e.g., metal traces) exposed in a top layer of the package substrate. The package substrate also includes one or more metallization layers that include metal interconnects (e.g., metal traces, metal lines) with vertical interconnect accesses (vias) coupling the metal interconnects together between adjacent metallization layers to provide electrical interfaces between the die(s). The package substrate also includes a bottom, outer metallization layer that includes metal interconnects coupled to external metal interconnects (e.g., ball grid array (BGA) interconnects, land grid array (LGA)) to provide an external interface between the die(s) in the IC package. The external metal interconnects can also be coupled (e.g., soldered) to traces in a printed circuit board (PCB) to attach the package to the PCB and interface its die(s) with the circuitry of the PCB. The die(s) may be mounted to the top layer of the package substrate through die interconnects. Other die(s) may also be mounted, utilizing die interconnects, to the bottom, outer metallization layer that includes metal interconnects between BGA interconnects. SUMMARY Aspects disclosed in the detailed description include an integrated circuit (IC) package having a package interconnect including a pillar and a solder cap coupled to a bottom surface of the pillar to reduce the height of the IC package. The IC package includes a substrate comprising an outer metallization layer having a metal pad and a package mold layer adjacent to the outer metallization layer. The pillar has a top surface and a bottom surface. The pillar extends through the package mold layer with the top surface coupled to the metal pad and the bottom surface coupled to the solder cap. In contrast to conventional package interconnects, such as ball grid arrays (BGAs), for example, deploying the solder cap on the bottom surface of the pillar advantageously results in using less solder and a tighter pitch between adjacent package interconnects because the width of the pillar is less than a solder ball in a BGA. Additionally, in contrast to costly package interconnect processes, such as package interconnects utilizing an electroless nickel immersion gold (ENIG) metal plating process, deploying the solder cap on the bottom surface of the pillar advantageously utilizes conventional packaging to produce a highly reliable solder joint without utilizing additional ENIG processes. In this regard in one aspect, an electronic device is disclosed. The electronic device comprises an integrated circuit (IC) package and a package interconnect. The IC package includes a substrate extending in a first direction which comprises an outer metallization layer having a metal pad and a package mold layer adjacent to the outer metallization layer. The package interconnect comprises a pillar extending in a second direction through the package mold layer. The pillar has a top surface and a bottom surface wherein the top surface coupled to the metal pad. The package interconnect also comprises a solder cap coupled to the bottom surface. In another aspect, a method for fabricating an electronic device is disclosed. The method includes forming an integrated circuit (IC) package and forming a package interconnect. Forming the integrated circuit (IC) package includes forming a substrate extending in a first direction wherein the substrate comprises an outer metallization layer having a metal pad and forming a package mold layer adjacent to the outer metallization layer. Forming the package interconnect includes forming a pillar extending in a second direction through the package mold layer wherein the pillar has a top surface and a bottom surface. The top surface is coupled to the metal pad. Forming the package interconnect also includes forming a solder cap coupled to the bottom surface. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a side view of an exemplary three-dimensional (3D) integrated circuit (IC) (3DIC) package that includes a package interconnect including solder balls in a ball grid array (BGA); FIG. 2 is a side view of an exemplary 3DIC package that includes a package interconnect including a pillar and a solder cap coupled to a bottom surface of the pillar to reduce the height of the 3DIC package; FIG. 3 is a side view of an exemplary electronic device including the 3DIC package in FIG. 2 coupled