US-20260130293-A1 - SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package includes an interposer chip on a package substrate, a first semiconductor chip on the interposer chip, and a second semiconductor chip on the interposer chip and horizontally spaced apart from the first semiconductor chip. The interposer chip is on the package substrate through first and second connection terminals. The first semiconductor chip is on the interposer chip through third connection terminals. The second semiconductor chip is on the interposer chip through fourth connection terminals. A width of the first connection terminals is the same as that of the third connection terminals. An interval between the first connection terminals is the same as that between the third connection terminals. A width of the second connection terminals is the same as that of the fourth connection terminals. An interval between the second connection terminals is the same as that between the fourth connection terminals.

Inventors

• Dongkuk Lee
• Seungduk Baek

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250623

Priority Date

20241106

Claims (20)

1. 1 . A semiconductor package, comprising: a package substrate; an interposer chip on the package substrate; a first semiconductor chip mounted on the interposer chip; and a second semiconductor chip mounted on the interposer chip and horizontally spaced apart from the first semiconductor chip, wherein the interposer chip is mounted on the package substrate through a plurality of first connection terminals and a plurality of second connection terminals, the first and second connection terminals being on a bottom surface of the interposer chip, wherein the first semiconductor chip is mounted on the interposer chip through a plurality of third connection terminals on a bottom surface of the first semiconductor chip, wherein the second semiconductor chip is mounted on the interposer chip through a plurality of fourth connection terminals on a bottom surface of the second semiconductor chip, wherein a first width of the plurality of first connection terminals is a same as a third width of the plurality of third connection terminals, wherein a first interval between the plurality of first connection terminals is a same as a third interval between the plurality of third connection terminals, wherein a second width of the plurality of second connection terminals is a same as a fourth width of the plurality of fourth connection terminals, and wherein a second interval between the plurality of second connection terminals is a same as a fourth interval between the plurality of fourth connection terminals.
2. 2 . The semiconductor package of claim 1 , wherein the bottom surface of the interposer chip comprises: a first region on which the plurality of first connection terminals are provided; and a second region on which the plurality of second connection terminals are provided, wherein a top surface of the interposer chip comprises: a third region on which the plurality of third connection terminals are provided; and a fourth region on which the plurality of fourth connection terminals are provided, wherein the first region vertically overlaps at least a portion of the third region, and wherein the second region vertically overlaps at least a portion of the fourth region.
3. 3 . The semiconductor package of claim 2 , wherein an arrangement of the plurality of first connection terminals is a same as an arrangement of the plurality of third connection terminals, and the arrangement of the plurality of first connection terminals and the arrangement of the plurality of third connection terminals are shifted, with respect to one another, in a first direction parallel to the top surface of the interposer chip.
4. 4 . The semiconductor package of claim 2 , wherein: each of the plurality of third connection terminals is positioned above and overlaps a corresponding one of the plurality of first connection terminals, and each of the plurality of fourth connection terminals is positioned above and overlaps a corresponding one of the plurality of second connection terminals.
5. 5 . The semiconductor package of claim 1 , wherein the bottom surface of the interposer chip comprises: a first region on which the plurality of first connection terminals are provided; a second region on which the plurality of second connection terminals are provided; and a third region that is an area other than the first region and the second region, wherein the interposer chip further comprises a plurality of dummy terminals on the bottom surface of the interposer chip and on the third region, wherein a fifth width of the plurality of dummy terminals is a same as the third width of the plurality of third connection terminals or the fourth width of the plurality of fourth connection terminals, and wherein a fifth interval between the dummy terminals is a same as the third interval between the third connection terminals or the fourth interval between the fourth connection terminals.
6. 6 . The semiconductor package of claim 5 , wherein: a sixth interval between a first dummy terminal of the plurality of dummy terminals and a third connection terminal of the plurality of third connection terminals, the first dummy terminal and the third connection terminal adjacent to one another, is 0.5 times to two times the third interval between the plurality of third connection terminals, and a seventh interval between a second dummy terminal of the plurality of dummy terminals and a fourth connection terminal of the plurality of fourth connection terminals, the second dummy terminal and the fourth connection terminal adjacent to one another, is 0.5 times to two times the fourth interval between the plurality of fourth connection terminals.
7. 7 . The semiconductor package of claim 1 , wherein the interposer chip comprises: a base layer; a plurality of through vias that extend in the base layer; and a plurality of lower pads on a bottom surface of the base layer, wherein the plurality of through vias are electrically coupled to the plurality of lower pads, and wherein the plurality of first connection terminals and the plurality of second connection terminals are coupled to the plurality of lower pads.
8. 8 . The semiconductor package of claim 7 , wherein the interposer chip comprises a redistribution layer on a top surface of the base layer, wherein the plurality of through vias are coupled to the redistribution layer, wherein the redistribution layer comprises a plurality of upper pads on a top surface of the redistribution layer, wherein the plurality of third connection terminals and the plurality of fourth connection terminals are electrically coupled to the plurality of upper pads, and wherein the plurality of upper pads are vertically aligned with the plurality of lower pads.
9. 9 . The semiconductor package of claim 7 , wherein the interposer chip further comprises a passive element on a top surface of the base layer.
10. 10 . The semiconductor package of claim 7 , wherein the base layer comprises a semiconductor substrate.
11. 11 . The semiconductor package of claim 1 , wherein: the plurality of first connection terminals and the plurality of third connection terminals are electrically connected to the first semiconductor chip, and the plurality of second connection terminals and the plurality of fourth connection terminals are electrically connected to the second semiconductor chip.
12. 12 . A semiconductor package, comprising: a package substrate; an interposer chip on the package substrate; a first semiconductor chip mounted on the interposer chip; a second semiconductor chip mounted on the interposer chip and horizontally spaced apart from the first semiconductor chip; a plurality of first connection terminals on a first region of a bottom surface of the interposer chip, wherein the plurality of first connection terminals electrically connect the interposer chip and the package substrate to one another; a plurality of second connection terminals on a second region of the bottom surface of the interposer chip, wherein the plurality of second connection terminals electrically connect the interposer chip and the package substrate to one another; a plurality of third connection terminals that electrically connect the interposer chip and the first semiconductor chip to one another; and a plurality of fourth connection terminals that electrically connect the interposer chip and the second semiconductor chip to one another, wherein a first width of the plurality of first connection terminals is a same as a third width of the plurality of third connection terminals, wherein a second width of the plurality of second connection terminals is a same as a fourth width of the plurality of fourth connection terminals, wherein the first region vertically overlaps the first semiconductor chip, and wherein the second region vertically overlaps the second semiconductor chip.
13. 13 . The semiconductor package of claim 12 , wherein: an interval between the plurality of first connection terminals is a same as an interval between the plurality of third connection terminals, and an interval between the plurality of second connection terminals is a same as an interval between the plurality of fourth connection terminals.
14. 14 . The semiconductor package of claim 12 , wherein a top surface of the interposer chip comprises: a third region on which the plurality of third connection terminals are provided; and a fourth region on which the plurality of fourth connection terminals are provided, wherein the first region vertically overlaps at least a portion of the third region, and wherein the second region vertically overlaps at least a portion of the fourth region.
15. 15 . The semiconductor package of claim 14 , wherein: an arrangement of the plurality of first connection terminals is a same as an arrangement of the plurality of third connection terminals, and the arrangement of the plurality of first connection terminals and the arrangement of the plurality of third connection terminals are shifted with respect to one another in a first direction parallel to the top surface of the interposer chip.
16. 16 . The semiconductor package of claim 12 , wherein: each of the plurality of third connection terminals is positioned above and overlaps a corresponding one of the plurality of first connection terminals, and each of the plurality of fourth connection terminals is positioned above and overlaps a corresponding one of the second connection terminals.
17. 17 . The semiconductor package of claim 12 , wherein: the bottom surface of the interposer chip further comprises a third region that is an area other than the first region and the second region, the interposer chip comprises a plurality of dummy terminals on the bottom surface of the interposer chip on the third region, a fifth width of the plurality of dummy terminals is a same as the third width of the plurality of third connection terminals or the fourth width of the plurality of fourth connection terminals, and an interval between the plurality of dummy terminals is a same as an interval between the plurality of third connection terminals or an interval between the plurality of fourth connection terminals.
18. 18 . The semiconductor package of claim 12 , wherein the interposer chip further comprises: a base layer; a plurality of through vias that extend vertically in the base layer; a plurality of lower pads on a bottom surface of the base layer, wherein the plurality of through vias are electrically coupled to the plurality of lower pads; and a passive element on a top surface of the base layer.
19. 19 . The semiconductor package of claim 12 , wherein: the plurality of first connection terminals and the plurality of third connection terminals are electrically connected to the first semiconductor chip, and the plurality of second connection terminals and the plurality of fourth connection terminals are electrically connected to the second semiconductor chip.
20. 20 . A semiconductor package, comprising: a package substrate; an interposer chip mounted on the package substrate through a plurality of dummy terminals, a plurality of first connection terminals, and a plurality of second connection terminals; a semiconductor chip mounted on the interposer chip through a plurality of third connection terminals; and a chip stack mounted on the interposer chip through a plurality of fourth connection terminals, wherein the plurality of first connection terminals and the plurality of third connection terminals are electrically connected to the semiconductor chip, wherein the plurality of second connection terminals and the plurality of fourth connection terminals are electrically connected to the chip stack, wherein a width of the plurality of first connection terminals is a same as a width of the plurality of third connection terminals, wherein a width of the plurality of second connection terminals is a same as a width of the plurality of fourth connection terminals, wherein each of the plurality of third connection terminals is positioned above and overlaps a corresponding one of the plurality of first connection terminals, wherein each of the plurality of fourth connection terminals is positioned above and overlaps a corresponding one of the plurality of second connection terminals, and wherein the plurality of dummy terminals are between the plurality of first connection terminals and the plurality of third connection terminals and are electrically insulated from the semiconductor chip and the chip stack.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2024-0156362 filed on Nov. 6, 2024 in the Korean Intellectual Property Office, the entirety of which is hereby incorporated by reference. BACKGROUND With the development of electronic industry, electronic products have increasingly demands for high performance, high speed, and compact size. To meet the trend, there has recently been developed a packaging technology in which a plurality of semiconductor chips are mounted in a single package. Portable devices have been increasingly demanded in recent electronic product markets, and as a result, it has been ceaselessly required for reduction in size and weight of electronic parts mounted on the portable devices. In order to accomplish the reduction in size and weight of the electronic parts, there is need for technology to integrate a number of individual devices into a single package as well as technology to reduce individual sizes of mounting parts. Various problems occur in association with an increase in stacking number of devices. SUMMARY Some aspects of the present disclosure provide semiconductor packages with improved structural stability. Some aspects of the present disclosure provide semiconductor packages with improved electrical properties. According to some implementations of the present disclosure, a semiconductor package may comprise: a package substrate; an interposer chip on the package substrate; a first semiconductor chip mounted on the interposer chip; and a second semiconductor chip mounted on the interposer chip and horizontally spaced apart from the first semiconductor chip. The interposer chip may be mounted on the package substrate through a plurality of first connection terminals and a plurality of second connection terminals, the first and second connection terminals being on a bottom surface of the interposer chip. The first semiconductor chip may be mounted on the interposer chip through a plurality of third connection terminals on a bottom surface of the first semiconductor chip. The second semiconductor chip may be mounted on the interposer chip through a plurality of fourth connection terminals on a bottom surface of the second semiconductor chip. A first width of the first connection terminals may be the same as a third width of the third connection terminals. A first interval between the first connection terminals may be the same as third interval between the third connection terminals. A second width of the second connection terminals may be the same as a fourth width of the fourth connection terminals. A second interval between the second connection terminals may be the same as a fourth interval between the fourth connection terminals. According to some implementations of the present disclosure, a semiconductor package may comprise: a package substrate; an interposer chip on the package substrate; a first semiconductor chip mounted on the interposer chip; a second semiconductor chip mounted on the interposer chip and horizontally spaced apart from the first semiconductor chip; a plurality of first connection terminals on a first region of a bottom surface of the interposer chip, the first connection terminals connecting the interposer chip and the package substrate to each other; a plurality of second connection terminals on a second region of the bottom surface of the interposer chip, the second connection terminals connecting the interposer chip and the package substrate to each other; a plurality of third connection terminals that connect the interposer chip and the first semiconductor chip to each other; and a plurality of fourth connection terminals that connect the interposer chip and the second semiconductor chip to each other. A first width of the first connection terminals may be the same as a third width of the third connection terminals. A second width of the second connection terminals may be the same as a fourth width of the fourth connection terminals. The first region may vertically overlap the first semiconductor chip. The second region may vertically overlap the second semiconductor chip. According to some implementations of the present disclosure, a semiconductor package may comprise: a package substrate; an interposer chip mounted on the package substrate through a plurality of dummy terminals, a plurality of first connection terminals, and a plurality of second connection terminals; a semiconductor chip mounted on the interposer chip through the third connection terminals; and a chip stack mounted on the interposer chip through the fourth connection terminals. The first and third connection terminals may be electrically connected to the semiconductor chip. The second and fourth connection terminals may be electrically connected to the chip stack. A width of the first connection terminals may be the same as a width of the third connection terminals. A width of the second connecti