US-20260130294-A1 - SEMICONDUCTOR PACKAGE

US20260130294A1US 20260130294 A1US20260130294 A1US 20260130294A1US-20260130294-A1

Abstract

Provided is a semiconductor package, including a lower redistribution layer structure including a lower redistribution layer, a lower semiconductor chip on the lower redistribution layer structure, the lower semiconductor chip connected to the lower redistribution layer, a sealing member on the lower semiconductor chip and the lower redistribution layer structure, a conductive post penetrating the sealing member, the conductive post connected to the lower redistribution layer, and an upper redistribution layer structure on an upper surface of the sealing member and an upper surface of the conductive post, the upper redistribution layer structure including an upper insulation layer and an upper redistribution layer, wherein a sidewall of the conductive post has a first uneven portion, and an upper surface of the conductive post has a second uneven portion, a roughness of the second uneven portion being different from a roughness of the first uneven portion.

Inventors

Gongje LEE
Kyungdon Mun

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251021
Priority Date: 20241107

Claims (20)

1 . A semiconductor package, comprising: a lower redistribution layer structure comprising a lower redistribution layer; a lower semiconductor chip on the lower redistribution layer structure, the lower semiconductor chip connected to the lower redistribution layer; a sealing member on the lower semiconductor chip and the lower redistribution layer structure; a conductive post penetrating the sealing member, the conductive post connected to the lower redistribution layer; and an upper redistribution layer structure on an upper surface of the sealing member and an upper surface of the conductive post, the upper redistribution layer structure comprising an upper insulation layer and an upper redistribution layer, wherein a sidewall of the conductive post has a first uneven portion, and the upper surface of the conductive post has a second uneven portion, a roughness of the second uneven portion being different from a roughness of the first uneven portion.
2 . The semiconductor package of claim 1 , wherein an arithmetic mean roughness of the second uneven portion is less than an arithmetic mean roughness of the first uneven portion.
3 . The semiconductor package of claim 1 , wherein an arithmetic mean roughness of the first uneven portion is in a range of 0.2 μm to 0.25 μm, and an arithmetic mean roughness of the second uneven portion is in a range of 0.05 μm to 0.1 μm.
4 . The semiconductor package of claim 1 , wherein the upper redistribution layer comprises a via contact and a wiring line.
5 . The semiconductor package of claim 4 , wherein a portion of the upper surface of the conductive post contacts the via contact at a lowermost portion of the upper redistribution layer structure, and a remaining portion of the upper surface of the conductive post contacts the upper insulation layer of the upper redistribution layer structure.
6 . The semiconductor package of claim 1 , wherein the upper insulation layer of the upper redistribution layer structure comprises a photosensitive insulation layer.
7 . The semiconductor package of claim 1 , the conductive post comprises copper.
8 . The semiconductor package of claim 1 , the sidewall of the conductive post contacts the sealing member.
9 . The semiconductor package of claim 1 , the sealing member comprises an epoxy mold compound (EMC).
10 . The semiconductor package of claim 1 , further comprising: an upper semiconductor package on the upper redistribution layer structure, the upper semiconductor package being connected to the upper redistribution layer structure; and a heat dissipation structure on the upper redistribution layer structure.
11 . A semiconductor package, comprising: a lower redistribution layer structure comprising a lower insulation layer, a lower redistribution layer, and a bonding pad; a lower semiconductor chip on the lower redistribution layer structure, the lower semiconductor chip being connected to the lower redistribution layer; a sealing member on the lower semiconductor chip and the lower redistribution layer structure; conductive post penetrating the sealing member and contacting the bonding pad of the lower redistribution layer, the conductive post being spaced apart from the lower semiconductor chip; an upper redistribution layer structure on an upper surface of the sealing member and an upper surface of the conductive post, and the upper redistribution layer structure comprising an upper insulation layer and an upper redistribution layer, the upper redistribution layer being connected to the conductive post; an upper semiconductor package on the upper redistribution layer structure, the upper semiconductor package being connected to the upper redistribution layer structure; and a heat dissipation structure on the upper redistribution layer structure, wherein a sidewall of the conductive post has a first uneven portion, and the upper surface of the conductive post has a second uneven portion, a roughness of the second uneven portion being different from a roughness of the first uneven portion.
12 . The semiconductor package of claim 11 , wherein an arithmetic mean roughness of the second uneven portion is less than an arithmetic mean roughness of the first uneven portion.
13 . The semiconductor package of claim 11 , wherein an arithmetic mean roughness of the first uneven portion is in a range of 0.2 μm to 0.25 μm, and an arithmetic mean roughness of the second uneven portion is within a range of 0.05 μm to 0.1 μm.
14 . The semiconductor package of claim 11 , wherein the upper redistribution layer comprises a via contact and a wiring line, and a portion of the upper surface of the conductive post contacts the via contact at a lowermost portion of the upper redistribution layer structure, and a remaining portion of the upper surface of the conductive post contacts the upper insulation layer of the upper redistribution layer structure.
15 . The semiconductor package of claim 11 , the conductive post comprises copper.
16 . The semiconductor package of claim 11 , the sidewall of the conductive post contacts the sealing member.
17 . The semiconductor package of claim 11 , the upper insulation layer at a lowermost portion of the upper redistribution layer structure contacts the upper surface of the conductive post and the upper surface of the sealing member.
18 . A semiconductor package, comprising: a lower redistribution layer structure comprising a lower insulation layer and a lower redistribution layer; an upper redistribution layer structure being spaced apart from the lower redistribution layer structure, the upper redistribution layer structure comprising an upper insulation layer and an upper redistribution layer; and a conductive post between the lower redistribution layer structure and the upper redistribution layer structure, wherein a sidewall of the conductive post has a first uneven portion, and the upper surface of the conductive post has a second uneven portion, a roughness of the second uneven portion being different from a roughness of the first uneven portion.
19 . The semiconductor package of claim 18 , further comprising a sealing member filling a space between the lower redistribution layer structure and the upper redistribution layer structure, wherein the first uneven portion of the sidewall of the conductive post contacts the sealing member, and the second uneven portion of the upper surface of the conductive post contacts the upper redistribution layer and the upper insulation layer.
20 . The semiconductor package of claim 18 , wherein an arithmetic mean roughness of the first uneven portion is in a range of 0.2 μm to 0.25 μm, and an arithmetic mean roughness of the second uneven portion is in a range of 0.05 μm to 0.1 μm.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to Korean Patent Application No. 10-2024-0156752, filed on Nov. 7, 2024, in the Korean Intellectual Property Office KIPO, the disclosure of which is incorporated herein in its entirety by reference. BACKGROUND 1. Field Embodiments of the present disclosure relate to a semiconductor package. Particularly, embodiments relate to a semiconductor package including a Fan Out Wafer Level Package (FOWPLP). 2. Description of Related Art In the Fan Out Wafer Level Package (FOWLP) technology, conductive posts having a pillar shape may be used to electrically connect an upper chip and a lower chip. However, since an adhesion property between the conductive posts and a sealing member and an adhesion property between the conductive posts and an insulation layer are not sufficient good, a delamination between the conductive posts and a sealing member and a delamination between the conductive posts and the insulation layer may occur. Accordingly, a failure of reliability of the semiconductor package may occur. SUMMARY One or more embodiments provide a semiconductor package having excellent characteristics. According to an aspect of one or more embodiments, there is provided a semiconductor package, including a lower redistribution layer structure including a lower redistribution layer, a lower semiconductor chip on the lower redistribution layer structure, the lower semiconductor chip connected to the lower redistribution layer, a sealing member on the lower semiconductor chip and the lower redistribution layer structure, a conductive post penetrating the sealing member, the conductive post connected to the lower redistribution layer, and an upper redistribution layer structure on an upper surface of the sealing member and an upper surface of the conductive post, the upper redistribution layer structure including an upper insulation layer and an upper redistribution layer, wherein a sidewall of the conductive post has a first uneven portion, and the upper surface of the conductive post has a second uneven portion, a roughness of the second uneven portion being different from a roughness of the first uneven portion. According to an aspect of one or more embodiments, there is provided a semiconductor package, including a lower redistribution layer structure including a lower insulation layer, a lower redistribution layer, and a bonding pad, a lower semiconductor chip on the lower redistribution layer structure, the lower semiconductor chip being connected to the lower redistribution layer, a sealing member on the lower semiconductor chip and the lower redistribution layer structure, a conductive post penetrating the sealing member and contacting the bonding pad of the lower redistribution layer, the conductive post being spaced apart from the lower semiconductor chip, an upper redistribution layer structure on an upper surface of the sealing member and an upper surface of the conductive post, and the upper redistribution layer structure including an upper insulation layer and an upper redistribution layer, the upper redistribution layer being connected to the conductive post, an upper semiconductor package on the upper redistribution layer structure, the upper semiconductor package being connected to the upper redistribution layer structure, and a heat dissipation structure on the upper redistribution layer structure, wherein a sidewall of the conductive post has a first uneven portion, and the upper surface of the conductive post has a second uneven portion, a roughness of the second uneven portion being different from a roughness of the first uneven portion. According to still another aspect of one or more embodiments, there is provided a semiconductor package, including a lower redistribution layer structure including a lower insulation layer and a lower redistribution layer, an upper redistribution layer structure being spaced apart from the lower redistribution layer structure, the upper redistribution layer structure including an upper insulation layer and an upper redistribution layer, and a conductive post between the lower redistribution layer structure and the upper redistribution layer structure, wherein a sidewall of the conductive post has a first uneven portion, and the upper surface of the conductive post has a second uneven portion, a roughness of the second uneven portion being different from a roughness of the first uneven portion. According to further still another aspect of one or more embodiments, there is provided method of manufacturing a semiconductor package, including forming a lower redistribution layer structure including a lower redistribution layer, forming a lower semiconductor chip on the lower redistribution layer structure, the lower semiconductor chip connected to the lower redistribution layer, forming a sealing member on the lower semiconductor chip and the lower redistribution layer structure, forming a conductive po