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US-RE50887-E1 - Testing circuitry in a stacked semiconductor device using through silicon vias

Abstract

A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.

Inventors

  • Yoshiro Riho

Assignees

  • LONGITUDE LICENSING LIMITED

Dates

Publication Date
20260512
Application Date
20230123
Priority Date
20090205

Claims (20)

  1. 1 . A method of testing a semiconductor device comprising; providing a first wafer that comprises a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode; providing a second wafer that comprises a second electrode penetrating the second wafer; stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer; probing a needle to the pad; and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.
  2. 2 . The method as claimed in claim 1 , wherein: a circuit to be tested is included in the second wafer; and the test signal is supplied to the circuit via the first electrode and the second electrode.
  3. 3 . The method as claimed in claim 2 , wherein the second wafer further comprises a switch that is formed between the second electrode and the circuit.
  4. 4 . The method as claimed in claim 3 , wherein the switch connects the second electrode with the circuit when the semiconductor device is under test.
  5. 5 . The method as claimed in claim 1 , wherein the pad is connected directly with the first electrode.
  6. 6 . The method as claimed in claim 5 , wherein the first wafer further comprises an electrostatic discharge (ESD) protection circuit that is connected directly with the first electrode.
  7. 7 . The method as claimed in claim 1 , wherein the providing the second wafer comprises stacking a plurality of wafers, each of the plurality of wafers having a substantially identical structure.
  8. 8 . The method as claimed in claim 1 , wherein the test signal is supplied to the needle, the test signal being supplied to the first electrode via the needle and the pad.
  9. 9 . A method of producing a tested semiconductor device comprising: forming a semiconductor device; and testing the semiconductor device, the testing including: stacking a first wafer onto a second wafer having the semiconductor device such that a first electrode formed on the first wafer is connected with a second electrode formed on the second wafer, the first electrode penetrating the first wafer, the second electrode penetrating the second wafer and being coupled electrically with the semiconductor device; and supplying a test signal to the first electrode of the first wafer to input the test signal into the semiconductor device via the first electrode and the second electrode.
  10. 10 . The method as claimed in claim 9 , wherein the second wafer comprises a switch that is formed between the second electrode and the semiconductor device.
  11. 11 . The method as claimed in claim 10 , wherein the switch connects the second electrode with the semiconductor device when the semiconductor device is under test.
  12. 12 . The method as claimed in claim 9 , wherein the testing further includes probing a needle to a pad that is formed on the first wafer and is coupled electrically with the first electrode.
  13. 13 . The method as claimed in claim 12 , wherein the test signal is supplied to the needle, the test signal being supplied to the first electrode via the needle and the pad.
  14. 14 . The method as claimed in claim 9 , wherein the first wafer comprises an electrostatic discharge (ESD) protection circuit that is connected directly with the first electrode.
  15. 15 . The method as claimed in claim 9 , wherein the second wafer comprises a plurality of stacked wafers, each of the plurality of stacked wafers having a substantially identical structure.
  16. 16 . A method of producing a semiconductor device comprising: stacking a plurality of semiconductor chips, wherein each of the plurality of semiconductor chips has already been tested by a testing method, the testing method including; stacking a first wafer onto a second wafer comprising the semiconductor chip such that a first electrode formed on the first wafer is connected with a second electrode formed on the second wafer, the first electrode penetrating the first wafer, the second electrode penetrating the second wafer and being connected electrically with the semiconductor chip; and supplying a test signal to the first electrode of the first wafer to input the test signal into the semiconductor chip via the first electrode and the second electrode.
  17. 17 . The method as claimed in claim 16 , wherein: a circuit to be tested is included in the semiconductor chip of the second wafer; and the test signal is supplied to the circuit via the first electrode and the second electrode.
  18. 18 . The method as claimed in claim 17 , wherein: the second wafer comprises a switch that is formed between the second electrode and the circuit; and the switch connects the second electrode with the circuit when the circuit is under test.
  19. 19 . The method as claimed in claim 16 , wherein the first wafer comprises an electrostatic discharge (ESD) protection circuit that is connected directly with the first electrode.
  20. 20 . The method as claimed in claim 16 , wherein the second wafer comprises a plurality of stacked wafers, each of the plurality of stacked wafers having a substantially identical structure.

Description

More than one reissue application has been filed for the reissue of Pat. No. 8,503,261. The reissue applications are application numbers the present application, Ser. No. 13/531,346 (issued as U.S. Pat. No. 8,503,261), Ser. No. 16/780,767 (issued as U.S. Pat. No. RE49390), and Ser. No. 14/820,325 (issued as U.S. Pat. No. RE47840). The present application is a reissue continuation of application Ser. No. 16/780,767, which is a reissue divisional of application Ser. No. 14/820,325, which is an application for reissue of U.S. Pat. No. 8,503,261, which is a Continuation Application of U.S. patent application Ser. No. 12/656,485, filed on Feb. 1, 2010 now U.S. Pat. No. 8,243,486, which is based on Japa-neseJapanese patent application No. 2009-024486, filed on Feb. 5, 2009, the entire contents of which is incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device having a DRAM or the like, and particularly to a semiconductor device formed by stacking a plurality of chip dies. 2. Description of the Related Art An example of this type of semiconductor devices is a semiconductor device in which a memory module is formed by stacking a plurality of DRAM chips on an IO chip mounted on an interposer board and connecting the DRAM chips to the IO chip by means of through electrodes TSVs formed within through silicon vias (Sivia) (see Japanese Laid-Open Patent Publication No. 2004-327474 (Patent Document 1) corresponding to U.S. Pat. No. 7,123,497 (Patent Document 2). More specifically, according to Patent Document 1, each of the DRAM chips of the memory module has a plurality of vias and through electrodes TSVs formed within these vias in order to transfer data signals and data mask signals accompanied by the data signals. A semiconductor device configured in this manner has advantages that the length of wiring lines connecting a plurality of DRAM chips can be shortened and a DLL, consuming a large amount of current, need be provided only on an IO I/O chip. SUMMARY However, Patent Document 1 gives no consideration to the case in which the transfer speed of a data signal output from a semiconductor device having a plurality of DRAM chips stacked is increased. Specifically, Patent Document 1 does not mention problems which may occur when the data transfer speed from the stacked DRAM chips is increased, nor does it mention solutions to such problems. In practice, it has been found that various problems such as increased power consumption and deteriorated decreased yield would occur when the data transfer speed from the DRAM chips is increased. Considering, for example, a case where a memory module having a total memory capacity of 2 GB (giga bytes) is formed of 16 DRAM chips, the memory module as a whole will have 64 data I/O through electrodes TSVs if each DRAM chip has four data I/O through electrodes TSVs. If it is assumed here that a data signal is input and output via each of the data I/O through electrodes TSVs at a transfer speed of 1600 Mbps, the data signal will be input and output via the data I/O through electrodes TSVs at a transfer speed of 102.4 Gbps (i.e., 12.8 GB/s) in the memory module as a whole. However, if a data signal is input and output to and from the DRAM chips at a data transfer speed of 1600 Mbps, the current consumed by the DRAM chips will be increased significantly, resulting in increased consumption current and noise in the memory module as a whole. Further, in order to realize a data transfer speed as high as 1600 Mbps, the DRAM chips must be operated at a high frequency of 800 MHz even if the DDR (Double Data Rate) technology is employed. Thus, the fabrication of DRAM chips operating at high frequency will impose difficulties in terms of various product specification values (e.g., timing specification), deteriorating the yield of the product. Furthermore, it will make it difficult to ensure stable operation of the memory module during communication with a memory controller. These problems are attributable to the face that as the number of stacked chips is increased, the high frequency operation (at high data transfer rate) is affected more by total parasitic resistance or total parasitic capacitance of the through silicon vias and via-to-via connections proportional to the thickness of the stacked chips. The present invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part. In one embodiment, a method of testing a semiconductor device comprising: providing a first wafer that comprises a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode; providing a second wafer that comprises a second electrode penetrating the second wafer; stacking the first wafe