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WO-2026090914-A1 - ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

WO2026090914A1WO 2026090914 A1WO2026090914 A1WO 2026090914A1WO-2026090914-A1

Abstract

An array substrate, a display panel and a display device. The array substrate comprises: a base (1); a plurality of gate lines (2); a plurality of data lines (3); a plurality of sub-pixel electrodes (4), each sub-pixel electrode (4) comprising a first pixel electrode portion (41) and a second pixel electrode portion (42); a plurality of first traces (5), each first trace (5) comprising a first sub-trace (51), the first sub-trace (51) being bent, and the orthographic projection of the first sub-trace (51) on the base (1) being located within the orthographic projection of each sub-pixel electrode (4) on the base (1); and a pixel circuit (6), the pixel circuit (6) being configured to release to the first traces (5) some of electrical signals loaded to the second pixel electrode portions (42), such that the brightness of the first pixel electrode portions (41) is greater than the brightness of the second pixel electrode portions (42).

Inventors

  • LUO, YANMEI
  • BAI, LU

Assignees

  • 京东方科技集团股份有限公司
  • 成都京东方显示科技有限公司

Dates

Publication Date
20260507
Application Date
20241030

Claims (20)

  1. An array substrate, comprising: Substrate; Multiple grid lines extend along the first direction; Multiple data lines extend along the second direction; Multiple sub-pixel electrodes, each sub-pixel electrode comprising: a first pixel electrode portion and a second pixel electrode portion; the first pixel electrode portion and the second pixel electrode portion of the same sub-pixel electrode are arranged along the second direction; Multiple first traces, each first trace including: a first sub-trace; the first sub-trace is bent and its orthographic projection on the substrate is located within the orthographic projection of the sub-pixel electrode on the substrate; the first sub-trace includes: a first sub-section and a second sub-section; the first sub-section extends along a first direction; one end of the second sub-section is connected to one end of the first sub-section and extends along a second direction, and the orthographic projection of the second sub-section on the substrate overlaps with the orthographic projection of the edge region of the sub-pixel electrode near the data line on the substrate; A pixel circuit is electrically connected to the first pixel electrode portion, the second pixel electrode portion, and the first trace. The pixel circuit is configured to release a portion of the electrical signal loaded onto the second pixel electrode portion to the first trace, so that the brightness of the first pixel electrode portion is greater than the brightness of the second pixel electrode portion.
  2. The array substrate of claim 1, wherein the first sub-trace further comprises: the third sub-part located on the side of the first sub-part away from the gate line, one end of which is connected to the other end of the first sub-part, and extending along the second direction; The first sub-part's orthographic projection on the substrate passes through the central region of the first pixel electrode's orthographic projection on the substrate; the second sub-part's orthographic projection on the substrate is located at the edge region on one side of the first pixel electrode's orthographic projection on the substrate; the third sub-part's orthographic projection on the substrate is located at the edge region on the other side of the first pixel electrode's orthographic projection on the substrate.
  3. The array substrate as claimed in claim 1 or 2, wherein the first sub-trace is on the substrate The orthographic projection of the bottom is located within the orthographic projection of the first pixel electrode portion onto the substrate; The array substrate further includes: a plurality of common traces; the plurality of common traces include: a first common trace; the orthographic projection of the first common trace on the substrate covers the orthographic projection of the first sub-trace on the substrate.
  4. The array substrate according to any one of claims 1-3, wherein the first trace further includes: a second sub-trace; the second sub-trace is located on the side of the first sub-part away from the gate line, one end of which is connected to the other end of the third sub-part, and extends along the first direction; The array substrate further includes: a second trace extending along the first direction; At least a portion of the second sub-trace's orthographic projection on the substrate overlaps with at least a portion of the second trace's orthographic projection on the substrate, and is electrically connected via a via at the overlap location.
  5. The array substrate as claimed in claim 4, wherein the second sub-trace includes: a second sub-trace main portion and a first transition portion; the first transition portion is connected to the end of the second sub-trace main portion; the width of the first transition portion in the second direction is greater than the width of the second sub-trace main portion in the second direction; The second trace includes: a second trace main portion extending along the first direction, and a second transition portion connected to the second trace main portion; the width of the second transition portion in the second direction is greater than the width of the second trace main portion in the second direction. The orthographic projection of the first adapter portion onto the substrate overlaps with the orthographic projection of the second adapter portion onto the substrate.
  6. The array substrate of claim 5, wherein the layer containing the first transition portion is located on the side of the layer containing the second transition portion away from the substrate; the array substrate further includes: a third transition portion located on the side of the layer containing the first transition portion away from the layer containing the second transition portion, and an insulating layer located between the layer containing the third transition portion and the layer containing the second transition portion. The insulating layer has a first through hole, which partially exposes the first adapter portion and partially exposes the second adapter portion. The third adapter portion covers the first through hole and partially contacts the first adapter portion and partially contacts the second adapter portion through the first through hole.
  7. The array substrate as claimed in claim 6, wherein the first common trace and the second... The traces and the gate lines are on the same layer and made of the same material; the first trace and the data line are on the same layer and made of the same material; the third adapter and the sub-pixel electrode are on the same layer and made of the same material.
  8. The array substrate as claimed in claim 7, wherein the first pixel electrode portion has a first recess at the position of the third transition portion; a portion of the third transition portion is located within the first recess. The second pixel electrode portion has a second recess at the position of the third transition portion; a portion of the third transition portion is located within the second recess.
  9. The array substrate as described in any one of claims 4-8, wherein the first trace further includes: a third sub-trace and a fourth sub-trace; the third sub-trace is located on the side of the first sub-part facing the gate line, one end of which is connected to the other end of the second sub-part and extends along the first direction; one end of the fourth sub-trace is connected to the other end of the third sub-trace, extends along the second direction, and its orthographic projection on the substrate intersects with the orthographic projection of the gate line on the substrate.
  10. The array substrate of claim 9, wherein the first trace further includes a fifth sub-trace; the fifth sub-trace extends along the first direction, and the other end of the fourth trace is connected to the middle position of the fifth sub-trace.
  11. The array substrate according to any one of claims 2-10, wherein the first trace further includes: a sixth sub-trace; the sixth sub-trace is connected to one end of the fifth sub-trace, and the orthographic projection of the sixth sub-trace on the substrate is located within the orthographic projection of the second pixel electrode portion on the substrate.
  12. The array substrate as claimed in claim 10 or 11, wherein the array substrate further comprises: a second common trace group; the second common trace group extends along the second direction and is disconnected at the location of the gate line; the second common trace group comprises: two second common traces located on different sides of the data line; The orthographic projection of the second common trace on the substrate overlaps with the orthographic projection of the sub-pixel electrode on the substrate.
  13. The array substrate of claim 12, further comprising: a third common trace; the third common trace extending along the first direction and intersecting with the data line, the... The first routing line is disconnected at the intersection.
  14. The array substrate of claim 13, wherein the orthographic projection of the fifth sub-trace onto the substrate is located within the orthographic projection of the substrate at the location where the third common trace is disconnected.
  15. The array substrate as described in any one of claims 4-10 and 12-14, wherein the orthographic projection of the first trace on the substrate does not overlap with the orthographic projection of the central region of the second pixel electrode portion on the substrate.
  16. The array substrate according to any one of claims 1-15, wherein the first pixel electrode portion and the second pixel electrode portion of the same sub-pixel electrode are respectively located on different sides of the gate line; and the area of the first pixel electrode portion projected onto the substrate is smaller than the area of the second pixel electrode portion projected onto the substrate.
  17. The array substrate according to any one of claims 1-16, wherein the pixel circuit comprises: a first transistor, a second transistor, and a third transistor; The first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first pixel electrode portion through a via. The first electrode of the second transistor is multiplexed with the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the second pixel electrode portion through a via. The first terminal of the third transistor is multiplexed with the second terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the first trace.
  18. The array substrate of claim 17, wherein the array substrate further comprises: a third wiring group; the third wiring group comprises: two third wirings extending along the first direction; and the region of the third wiring group located between the first pixel electrode portion and the second pixel electrode portion in the orthographic projection of the substrate is within the orthographic projection of the substrate. The orthographic projection of the third trace onto the substrate overlaps with the orthographic projection of at least a portion of the edge of the gate line onto the substrate; in the same group of third traces, the orthographic projection of the gap region between two third traces onto the substrate overlaps with the orthographic projection of the middle region of the gate line onto the substrate.
  19. The array substrate as claimed in claim 18, wherein, in the same third trace group, the orthographic projection of the third trace adjacent to the second pixel electrode portion on the substrate, in relation to the third... The second electrode of the two transistor is disconnected at the location where the orthographic projection of the substrate intersects.
  20. The array substrate as claimed in claim 18 or 19, wherein the array substrate further comprises: a fourth trace; the fourth trace extends along the second direction, and the region of the fourth trace located between two adjacent sub-pixel electrodes in the first direction is within the orthogonal projection of the substrate. The orthographic projection of the fourth trace on the substrate overlaps with the orthographic projection of the data line on the substrate.

Description

Array substrate, display panel and display device Technical Field This invention relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention This disclosure provides an array substrate, a display panel, and a display device. The array substrate includes: Substrate; Multiple grid lines extend along the first direction; Multiple data lines extend along the second direction; Multiple sub-pixel electrodes, each sub-pixel electrode comprising: a first pixel electrode portion and a second pixel electrode portion; the first pixel electrode portion and the second pixel electrode portion of the same sub-pixel electrode are arranged along the second direction; Multiple first traces, each first trace including a first sub-trace; the first sub-trace is bent and, in its orthographic projection onto the substrate, is located within the orthographic projection of the sub-pixel electrode onto the substrate; The first sub-trace includes: a first sub-part and a second sub-part; the first sub-part extends along the first direction; one end of the second sub-part is connected to one end of the first sub-part and extends along the second direction, and the orthographic projection of the second sub-part on the substrate overlaps with the orthographic projection of the edge region of the sub-pixel electrode near the data line on the substrate. A pixel circuit is electrically connected to the first pixel electrode portion, the second pixel electrode portion, and the first trace. The pixel circuit is configured to release a portion of the electrical signal loaded onto the second pixel electrode portion to the first trace, so that the brightness of the first pixel electrode portion is greater than the brightness of the second pixel electrode portion. In one possible implementation, the first sub-trace further includes: the third sub-part located on the side of the first sub-part away from the gate line, one end of which is connected to the other end of the first sub-part, and extending along the second direction; The first sub-part's orthographic projection on the substrate passes through the central region of the first pixel electrode's orthographic projection on the substrate; the second sub-part's orthographic projection on the substrate is located at the edge region on one side of the first pixel electrode's orthographic projection on the substrate; the third sub-part's orthographic projection on the substrate is located at the edge region on the other side of the first pixel electrode's orthographic projection on the substrate. In one possible implementation, the orthographic projection of the first sub-trace onto the substrate is located within the orthographic projection of the first pixel electrode portion onto the substrate. The array substrate further includes: a plurality of common traces; the plurality of common traces include: a first common trace; the orthographic projection of the first common trace on the substrate covers the orthographic projection of the first sub-trace on the substrate. In one possible implementation, the first trace further includes: a second sub-trace; the second sub-trace is located on the side of the first sub-part away from the gate line, one end of which is connected to the other end of the third sub-part, and extends along the first direction; The multiple common routes also include: a second route extending along the first direction; At least a portion of the second sub-trace's orthographic projection on the substrate overlaps with at least a portion of the second trace's orthographic projection on the substrate, and is electrically connected via a via at the overlap location. In one possible implementation, the second sub-trace includes: a second sub-trace main portion, to... and a first adapter portion; the first adapter portion is connected to the end of the second sub-trace main portion; the width of the first adapter portion in the second direction is greater than the width of the second sub-trace main portion in the second direction; The second trace includes: a second trace main portion extending al