WO-2026091087-A1 - DISPLAY SUBSTRATE AND DISPLAY DEVICE

Abstract

A display substrate and a display device. The display substrate comprises: a display area (AA) and a non-display area arranged around at least one side of the display area (AA), wherein the non-display area is provided with a gate drive circuit. The gate drive circuit (GOA) comprises: a plurality of cascaded shift registers, wherein at least two stages of shift registers among the plurality of cascaded shift registers are at least partially symmetrically arranged with respect to a straight line extending in a first direction (D1), and a second direction is an arrangement direction of the at least two stages of shift registers among the plurality of cascaded shift registers. The display substrate further comprises: two fourth power supply lines, wherein the orthographic projection of a first fourth power supply line (VL4-1) on a base is located between the orthographic projections of at least two transistors within at least one stage of shift register on the base, and the orthographic projection of a second fourth power supply line (VL4-2) on the base is located on the side, close to the display area, of the orthographic projections of a plurality of transistors within the at least one stage of shift register on the base.

Inventors

• WU, Zhongshan
• WANG, XIAOYUAN
• YANG, KUN
• GUO, JIANDONG
• PU, Xun
• YANG, GUODONG

Assignees

• 京东方科技集团股份有限公司
• 重庆京东方光电科技有限公司

Dates

Publication Date

20260507

Application Date

20241101

Claims (20)

1. A display substrate includes: a substrate having a display area and a non-display area surrounding at least one side of the display area, the non-display area including: a transistor device area having a gate driving circuit, the gate driving circuit including: a plurality of cascaded shift registers, at least one shift register including: a plurality of transistors and a fourth power supply terminal; At least two of the multiple cascaded shift registers are arranged at least partially symmetrically with respect to a straight line extending along a first direction, and the second direction is the arrangement direction of at least two of the multiple cascaded shift registers. The first direction and the second direction are located in the same plane and intersect. The display substrate further includes: two fourth power lines located in the transistor device area, the fourth power lines extending at least partially along the second direction; the fourth power lines are electrically connected to the fourth power terminal of at least one level shift register; The first fourth power line and its orthographic projection on the substrate are located between the orthographic projections of at least two transistors in at least one level shift register on the substrate, and the second fourth power line and its orthographic projection on the substrate are located on the side of the orthographic projections of multiple transistors in at least one level shift register closer to the display area.
2. The display substrate according to claim 1 further includes: a first power connection line and a second power connection line located in the non-display area, wherein at least one of the first power connection line and the second power connection line extends at least partially along a first direction; The first power connection line is electrically connected to the first end of the first fourth power line and the first end of the second fourth power line, respectively. The second power connection line is electrically connected to the second end of the first fourth power line and the second end of the second fourth power line, respectively.
3. According to claim 1, the display substrate, wherein the at least one shift register comprises: a sixth transistor, a fifteenth transistor, an eighteenth transistor, a second reset signal terminal, a drive signal output terminal, a first pull-down node, and a second pull-down node, wherein the control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the drive signal output terminal, and the second electrode of the sixth transistor is electrically connected to the fourth power supply terminal; the control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fifteenth transistor is electrically connected to the fourth power supply terminal; the control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the drive signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the fourth power supply terminal. The orthographic projection of the sixth transistor on the substrate is located between the orthographic projection of the second fourth power line on the substrate and the orthographic projection of the first fourth power line on the substrate, and the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the second fourth power line on the substrate is less than the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the first fourth power line on the substrate. The orthographic projection of at least one of the fifteenth and eighteenth transistors on the substrate is located on the side of the first fourth power line away from the display area, and the distance between the orthographic projection of at least one of the fifteenth and eighteenth transistors on the substrate and the orthographic projection of the first fourth power line on the substrate is less than the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the first fourth power line on the substrate.
4. According to claim 3, the display substrate further comprises a plurality of sub-pixels, at least one of the plurality of sub-pixels comprising: a first electrode and a second electrode, wherein the first electrode and the second electrode are transparent electrodes, and at least one of the plurality of transistors comprises: a control electrode, an active pattern, a first electrode and a second electrode; The display substrate further includes: a circuit structure layer disposed on the substrate; the circuit structure layer includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate; The first conductive layer includes: a fourth power line and a control electrode of at least one transistor among a plurality of transistors located in at least one level shift register; The semiconductor layer includes: an active pattern of at least one transistor among a plurality of transistors located in at least one level shift register; The second conductive layer includes: a first terminal and a second terminal of at least one of a plurality of transistors located in at least one level shift register; The third conductive layer includes: one of the first electrode and the second electrode located in at least one sub-pixel; The fourth conductive layer includes another electrode located in the first electrode and the second electrode of at least one sub-pixel.
5. The display substrate according to claim 4 further includes: a first power connection line and a second power connection line located in the non-display area; At least one of the first power connection line and the second power connection line is located in the first conductive layer.
6. According to claim 4, the display substrate, wherein at least one of the plurality of cascaded shift registers comprises: a capacitor, a pull-up node, and a drive signal output terminal, wherein the first terminal of the capacitor is electrically connected to the pull-up node, and the second terminal of the capacitor is electrically connected to the drive signal output terminal; At least one of the multiple cascaded shift registers includes: a first plate, a second plate, and a third plate, wherein at least two of the first plate, the second plate, and the third plate are disposed in different layers, and the orthographic projections of the first plate, the second plate, and the third plate onto the substrate at least partially overlap. The first electrode plate is electrically connected to the third electrode plate and serves as the first electrode of the capacitor, while the second electrode plate serves as the second electrode of the capacitor.
7. According to the display substrate of claim 6, at least one of the plurality of cascaded shift registers further includes: a first connecting part and a second connecting part, wherein the first electrode plate and the third electrode plate are connected through the first connecting part, and the second electrode plate is connected to the second connecting part; The first electrode plate is located in the first conductive layer, the second electrode plate and the first connecting portion are located in the second conductive layer, and the third electrode plate and the second connecting portion are disposed in the same layer and are located in the third conductive layer or the fourth conductive layer.
8. According to claim 4, the display substrate, wherein at least one of the plurality of cascaded shift registers comprises: a capacitor, a pull-up node, and a drive signal output terminal, wherein the first terminal of the capacitor is electrically connected to the pull-up node, and the second terminal of the capacitor is electrically connected to the drive signal output terminal; At least one of the multiple cascaded shift registers includes: a first plate, a second plate, a third plate, and a fourth plate, wherein at least two of the first plate, the second plate, the third plate, and the fourth plate are arranged in different layers, and the orthographic projections of at least two of the first plate, the second plate, the third plate, and the fourth plate on the substrate at least partially overlap. The first electrode plate is electrically connected to the fourth electrode plate and serves as the first electrode of the capacitor. The second electrode plate is electrically connected to the third electrode plate and serves as the second electrode of the capacitor.
9. According to claim 8, the display substrate, wherein at least one of the plurality of cascaded shift registers further comprises: a first connecting portion and a second connecting portion, wherein the first electrode plate and the fourth electrode plate are connected by the... The first connecting part is connected, and the second electrode plate and the third electrode plate are connected through the second connecting part; The first electrode plate is located in the first conductive layer, the second electrode plate and the first connecting portion are located in the second conductive layer, the third electrode plate is located in the third conductive layer, and the fourth electrode plate and the second connecting portion are located in the fourth conductive layer.
10. According to claim 4, the display substrate, wherein at least one of the plurality of cascaded shift registers comprises: a capacitor, a pull-up node, and a drive signal output terminal, wherein the first terminal of the capacitor is electrically connected to the pull-up node, and the second terminal of the capacitor is electrically connected to the drive signal output terminal; At least one of the multiple cascaded shift registers includes: a first plate, a second plate, a third plate, a fourth plate, and a fifth plate, wherein at least two of the first plate, the second plate, the third plate, the fourth plate, and the fifth plate are arranged in different layers, and the orthographic projections of at least two of the first plate, the second plate, the third plate, the fourth plate, and the fifth plate onto the substrate at least partially overlap; The first electrode plate is electrically connected to the third electrode plate and the fifth electrode plate respectively, and serves as the first electrode of the capacitor. The second electrode plate is electrically connected to the fourth electrode plate, and serves as the second electrode of the capacitor.
11. According to claim 10, the display substrate further includes a fifth conductive layer, wherein the fifth conductive layer is located between the semiconductor layer and the third conductive layer; The first electrode plate is located in the first conductive layer, the second electrode plate is located in the second conductive layer, the third electrode plate is located in the fifth conductive layer, the fourth electrode plate is located in the third conductive layer, and the fifth electrode plate is located in the fourth conductive layer.
12. The display substrate according to claim 1 further includes: a plurality of third power lines located in the transistor device region, wherein at least one of the plurality of third power lines extends at least partially along a first direction; The at least one shift register further includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a sixteenth transistor, a seventeenth transistor, and a third power supply terminal, wherein the second terminals of the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the sixteenth transistor, and the seventeenth transistor are respectively electrically connected to the third power supply terminal; At least one third power supply line is electrically connected to the third power supply terminal in at least one shift register.
13. According to the display substrate of claim 12, the plurality of cascaded shift registers include: a first shift register, a second shift register and a third shift register, wherein the first shift register is at least one of the plurality of cascaded shift registers, the second shift register is a shift register of one adjacent level of the first shift register, and the third shift register is a shift register of another adjacent level of the first shift register. At least one third power line is located between the first shift register and the second shift register, and is electrically connected to the third power supply terminal of the first shift register and the third power supply terminal of the second shift register. The center line of the at least one third power line extending in the first direction is the same as the center line of the first shift register and the second shift register extending in the first direction. At least one third power line is integrally structured with the second terminals of the fourth, fifth, eighth, ninth, eleventh, twelfth, thirteenth, fourteenth, sixteenth, and seventeenth transistors in at least one of the first and second shift registers.
14. According to claim 1, the display substrate further includes: a tenth... The fifth and eighteenth transistors are connected as follows: the control terminal of the fourth transistor is electrically connected to the blanking reset signal terminal; the first terminal of the fourth transistor is electrically connected to the pull-up node; and the second terminal of the fourth transistor is electrically connected to the third power supply terminal. The control terminal of the fifth transistor is electrically connected to the first reset signal terminal; the first terminal of the fifth transistor is electrically connected to the pull-up node; and the second terminal of the fifth transistor is electrically connected to the third power supply terminal. The control terminal of the eighth transistor is electrically connected to the signal input terminal; the first terminal of the eighth transistor is electrically connected to the first pull-down node; and the second terminal of the eighth transistor is electrically connected to the third power supply terminal. The control terminal of the ninth transistor is electrically connected to the pull-up node; the first terminal of the ninth transistor is electrically connected to the first pull-down node; and the second terminal of the ninth transistor is electrically connected to the third power supply terminal. The control terminal of the eleventh transistor is electrically connected to the signal input terminal; the first terminal of the eleventh transistor is electrically connected to the second pull-down node; and the second terminal of the eleventh transistor is electrically connected to the third power supply terminal. The control terminal of the twelfth transistor is electrically connected to the pull-up node; the first terminal of the twelfth transistor is electrically connected to the second pull-down node; and the second terminal of the thirteenth transistor is electrically connected to the third power supply terminal. The control electrode of the body transistor is electrically connected to the first pull-down node; the first electrode of the thirteenth transistor is electrically connected to the pull-up node; the second electrode of the thirteenth transistor is electrically connected to the third power supply terminal; the control electrode of the fourteenth transistor is electrically connected to the first pull-down node; the first electrode of the fourteenth transistor is electrically connected to the cascade signal output terminal; the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; the control electrode of the fifteenth transistor is electrically connected to the second pull-down node; the first electrode of the fifteenth transistor is electrically connected to the drive signal output terminal; the second electrode of the fifteenth transistor is electrically connected to the fourth power supply terminal; the control electrode of the sixteenth transistor is electrically connected to the second pull-down node; the first electrode of the sixteenth transistor is electrically connected to the pull-up node; the second electrode of the sixteenth transistor is electrically connected to the third power supply terminal; the control electrode of the seventeenth transistor is electrically connected to the second pull-down node; the first electrode of the seventeenth transistor is electrically connected to the cascade signal output terminal; the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; the control electrode of the eighteenth transistor is electrically connected to the second pull-down node; the first electrode of the eighteenth transistor is electrically connected to the drive signal output terminal; the second electrode of the eighteenth transistor is electrically connected to the third power supply terminal. The fourth transistor, the ninth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the eighth transistor are arranged sequentially along the first direction; The eighth and eleventh transistors are arranged along the second direction, the thirteenth and sixteenth transistors are arranged along the second direction, the fourteenth and seventeenth transistors are arranged along the second direction, and the fifteenth and eighteenth transistors are arranged along the second direction.
15. According to the display substrate of claim 14, the control electrode of the ninth transistor and the control electrode of the twelfth transistor are the same electrode, and the active pattern of the ninth transistor and the active pattern of the twelfth transistor are the same active pattern. The ninth transistor has two electrodes, and the twelfth transistor has two electrodes. The electrodes of the ninth and twelfth transistors are arranged along the first direction, and one of the electrodes of the ninth transistor and one of the electrodes of the twelfth transistor are the same electrode. The first terminal of the ninth transistor is located between the second terminals of the two ninth transistors, and the first terminal of the twelfth transistor is located between the second terminals of the two twelfth transistors; The second terminals of the ninth transistor and the twelfth transistor of at least one shift register are each connected to at least one third power supply line.
16. According to the display substrate of claim 14, the control electrode of the eighth transistor and the control electrode of the eleventh transistor are the same electrode, and the active pattern of the eighth transistor and the active pattern of the eleventh transistor are the same active pattern. The second electrode of the eighth transistor is the same as the second electrode of the eleventh transistor.
17. According to claim 14, the control electrode of the thirteenth transistor, the control electrode of the fourteenth transistor, and the control electrode of the fifteenth transistor are the same electrode; The control electrodes of the sixteenth, seventeenth, and eighteenth transistors are on the same electrode.
18. According to claim 1, the display substrate further includes: a first signal line area and a second signal line area, and at least one level shift register includes: a clock signal terminal, a first power supply terminal and a second power supply terminal; The first signal line area is located on the side of the transistor device area away from the display area, and the second signal line area is located on the side of the transistor device area closer to the display area. The first signal line area includes: multiple clock signal lines, a first power line, and a second power line; at least one of the multiple clock signal lines, the first power line, and the second power line extends at least partially along the second direction; The clock signal terminal of the at least one level shift register is electrically connected to one of the multiple clock signal lines, the first power line is electrically connected to the first power supply terminal of the at least one level shift register, and the second power supply line is electrically connected to the second power supply terminal of the at least one level shift register. The second signal line area includes a common signal line group, which includes at least one common signal line that extends at least partially along the second direction.
19. According to the display substrate of claim 18, the non-display area is further provided with a plurality of driving signal output lines located in the second conductive layer and a plurality of scan lines located in the first conductive layer, wherein at least one of the plurality of driving signal output lines is electrically connected to the driving signal output terminal of at least one level shift register and one of the plurality of scan lines. The drive signal output line includes: a first output section, a second output section and a third output section, wherein the second output section is connected to the first output section and the third output section respectively, the first output section extends along a first direction, and the second output section and the third output section extend along a second direction, wherein the first output section and the second output section are arranged at right angles. The second output and the third output in the drive signal output line connected to at least one shift register are located on the side of the first output that is away from the first adjacent shift register; The orthographic projection of the first output unit on the substrate at least partially overlaps with the orthographic projection of the at least one common signal line on the substrate, the orthographic projection of the third output unit on the substrate at least partially overlaps with the orthographic projection of the scan line on the substrate, and the orthographic projection of the second output unit on the substrate does not overlap with the orthographic projection of the scan line on the substrate.
20. According to claim 19, the display substrate, wherein the plurality of cascaded shift registers include: a first shift register, a second shift register, and a third shift register, wherein the first shift register is at least one of the plurality of cascaded shift registers, the second shift register is a shift register of one adjacent level of the first shift register, and the third shift register is a shift register of another adjacent level of the first shift register. The scan line connected to the first shift register and the scan line connected to the second shift register are at least partially symmetrical with respect to an axis of symmetry extending along a first direction between the first shift register and the second shift register; The spacing between the scan line connected to the first shift register and the scan line connected to the second shift register is greater than the spacing between the scan line connected to the first shift register and the scan line connected to the third shift register, and is greater than the length of at least one shift register extending along the second direction; At least one of the multiple cascaded shift registers includes: a first transistor to the Mth transistor and a first capacitor to the Nth capacitor; The m-th transistor in the first shift register and the m-th transistor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction of the first shift register and the second shift register, where m is any value from 1 to M. The nth capacitor in the first shift register and the nth capacitor in the second shift register are symmetrically arranged with respect to the midline extending along the first direction of the first shift register and the second shift register, where n is any value from 1 to N.

Description

Display substrate and display device Technical Field This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology Liquid crystal displays (LCDs) have experienced rapid development due to their small size, low power consumption, and lack of radiation. An LCD panel consists of a thin-film transistor array (TFT) substrate (cells) and a color filter (CF) substrate. Liquid crystal (LC) molecules are disposed between the array substrate and the color filter substrate. By controlling the common electrode and pixel electrode, an electric field is formed to drive the deflection of the liquid crystals, achieving grayscale display. Summary of the Invention The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims. In a first aspect, this disclosure provides a display substrate, comprising: a substrate having a display area and a non-display area surrounding at least one side of the display area, the non-display area comprising: a transistor device area having a gate driving circuit disposed thereon, the gate driving circuit comprising: a plurality of cascaded shift registers, at least one shift register comprising: a plurality of transistors and a fourth power supply terminal; At least two of the multiple cascaded shift registers are arranged at least partially symmetrically with respect to a straight line extending along a first direction, and the second direction is the arrangement direction of at least two of the multiple cascaded shift registers. The first direction and the second direction are located in the same plane and intersect. The display substrate further includes: two fourth power lines located in the transistor device area, the fourth power lines extending at least partially along the second direction; the fourth power lines are electrically connected to the fourth power terminal of at least one level shift register; The first fourth power line and its orthographic projection on the substrate are located between the orthographic projections of at least two transistors in at least one level shift register on the substrate, and the second fourth power line and its orthographic projection on the substrate are located on the side of the orthographic projections of multiple transistors in at least one level shift register closer to the display area. In an exemplary embodiment, it further includes: a first power connection line and a second power connection line located in the non-display area, wherein at least one of the first power connection line and the second power connection line extends at least partially along a first direction; The first power connection line is electrically connected to the first end of the first fourth power line and the first end of the second fourth power line, respectively. The second power connection line is electrically connected to the second end of the first fourth power line and the second end of the second fourth power line, respectively. In an exemplary embodiment, the at least one shift register includes: a sixth transistor, a fifteenth transistor, an eighteenth transistor, a second reset signal terminal, a drive signal output terminal, a first pull-down node, and a second pull-down node. The control terminal of the sixth transistor is electrically connected to the second reset signal terminal, the first terminal of the sixth transistor is electrically connected to the drive signal output terminal, and the second terminal of the sixth transistor is electrically connected to the fourth power supply terminal. The control terminal of the fifteenth transistor is electrically connected to the first pull-down node, the first terminal of the fifteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the fifteenth transistor is electrically connected to the fourth power supply terminal. The control terminal of the eighteenth transistor is electrically connected to the second pull-down node, and the first terminal of the eighteenth transistor is electrically connected to the second pull-down node. The drive signal output terminal is electrically connected, and the second terminal of the eighteenth transistor is electrically connected to the fourth power supply terminal; The orthographic projection of the sixth transistor on the substrate is located between the orthographic projection of the second fourth power line on the substrate and the orthographic projection of the first fourth power line on the substrate, and the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the second fourth power line on the substrate is less than the distance between the orthographic projection of the sixth transistor on the substrate and the orthographic projection of the first f