WO-2026091171-A1 - DISPLAY PANEL AND DISPLAY APPARATUS

WO2026091171A1WO 2026091171 A1WO2026091171 A1WO 2026091171A1WO-2026091171-A1

Abstract

A display panel (100) and a display apparatus. A gate driving unit (200a) of the display panel (100) comprises an output circuit (222), a receiving circuit (221) and a storage capacitor that are connected to each other, wherein the output circuit (222) and the receiving circuit (221) each comprise a gate transistor, with an active portion of the gate transistor being located in a first active layer (123); one electrode plate of the storage capacitor is located in a second active layer (127), and a gate of the gate transistor and the other electrode plate of the storage capacitor are located in a first gate layer (125); and the first gate layer (125), the first active layer (123) and the second active layer (127) are all arranged in different layers.

Inventors

ZHANG, YUHENG
LIU, HANG

Assignees

武汉华星光电半导体显示技术有限公司

Dates

Publication Date: 20260507
Application Date: 20241108
Priority Date: 20241104

Claims (20)

A display panel includes a plurality of gate driving units, each gate driving unit including an output circuit, a receiving circuit and a storage capacitor connected to each other, the output circuit including a first output transistor and a second output transistor connected to each other, the drain of the first output transistor being connected to a clock line, the drain of the second output transistor being connected to a high potential line, and the area of the first output transistor being larger than the area of the second output transistor. The output circuit and the receiving circuit both include a gate transistor. The active portion of the gate transistor is located in the first active layer. One plate of the storage capacitor is located in the second active layer. The gate of the gate transistor and the other plate of the storage capacitor are located in the first gate layer. The first gate layer, the first active layer, and the second active layer are all disposed in different layers.
According to claim 1, the display panel, wherein the receiving circuit includes a first node control module, and the first output transistor and the first node control module are connected to the first node; The storage capacitor includes a first capacitor, which includes a first plate and a second plate. The first plate is connected to the source of the first output transistor, and the second plate is connected to the first node. The first plate is located in the second active layer, and the second plate is located in the first gate layer.
According to claim 2, the display panel, wherein the receiving circuit includes a second node control module, and the second output transistor and the second node control module are connected to the second node; The storage capacitor includes a second capacitor, which includes a third plate and a fourth plate. The third plate is connected to the high-potential line, and the fourth plate is connected to the second node. The third plate is located in the second active layer, and the fourth plate is located in the first gate layer.
According to claim 3, the overlapping area of the first electrode plate and the second electrode plate is greater than the overlapping area of the third electrode plate and the fourth electrode plate.
According to claim 3, the display panel, wherein the first gate layer includes a first gate of the first output transistor and a second gate of the second output transistor, and the first gate and the second gate are arranged in a first direction; The area of the first gate is larger than the area of the second gate.
According to the display panel of claim 5, the first gate includes a first main gate and at least two first branch gates connected to the first main gate, the first main gate extends along the first direction, the first branch gates extend along the second direction, and the at least two first branch gates are spaced apart in the first direction. The second gate includes a second main gate and a second branch gate connected to the second main gate. The second main gate and the second branch gate extend along the second direction, and the first branch gate and the second branch gate are spaced apart in the first direction. The first main gate and the second branch gate are also spaced apart in the first direction. Wherein, the first main gate and a portion of the first branch gate are multiplexed as the second electrode plate, the second main gate and at most a portion of the second branch gate are multiplexed as the fourth electrode plate, the second direction is parallel to the scan line of the display panel, and the angle between the first direction and the second direction is greater than 0° and less than or equal to 90°.
According to the display panel of claim 6, the first active layer includes a first active portion of the first output transistor and a second active portion of the second output transistor, the first active portion and the second active portion both extend along the first direction, and the first active portion and the second active portion are connected. The first active portion overlaps with multiple first branch gates, and the second active portion overlaps with multiple second branch gates.
The display panel according to claim 7, wherein, in the second direction, the width of the first active portion is greater than the width of the second active portion.
According to claim 6, the display panel, wherein the second active layer includes the first electrode plate of the first capacitor and the third electrode plate of the second capacitor; Wherein, at least a portion of the outer contour of the first electrode plate is wider than the outer contour of the second electrode plate, and at least a portion of the outer contour of the third electrode plate is wider than the outer contour of the fourth electrode plate.
According to the display panel of claim 9, the second electrode plate includes a first main electrode plate and at least two first branch electrode plates connected to the first main electrode plate, the first main electrode plate extends along the first direction, the at least two first branch electrode plates extend along the second direction, and the plurality of first branch electrode plates are spaced apart in the first direction. Wherein, the first main plate overlaps at least partially with the first main gate, the first branch plate overlaps at least partially with the corresponding first branch gate, and the length of the first branch plate is less than the length of the first branch gate.
According to claim 6, the display panel further includes a first source/drain layer disposed on the side of the second active layer away from the first active layer, the first source/drain layer comprising: The first output transistor has a first source and a first drain, wherein the first drain includes a first branch drain and the first source includes a first branch source; The second output transistor has a second source and a second drain, the second drain includes a second branch drain, and the second source includes a second branch source. The first branch drain, the first branch source, the second branch drain, and the second branch drain all extend along the second direction and are arranged at intervals along the first direction. The first branch gate has a first branch drain and a first branch source on both sides of the second direction, and the second branch gate has a second branch drain and a second branch source on both sides of the second direction, and the second branch source near the first output transistor is multiplexed as the first branch source.
According to the display panel of claim 11, wherein the first source-drain layer further includes a source trunk extending along the first direction, the first branch source is connected to the source trunk, and at least a portion of the source trunk overlaps with the first capacitor.
According to claim 11, the display panel further includes a second source-drain layer disposed on the side of the first source-drain layer away from the first active layer, the second source-drain layer including a low-potential line and a high-potential line, the low-potential line and the high-potential line extending along the first direction and arranged along the second direction; The high-potential line overlaps with the output circuit, and the low-potential line overlaps with the receiving circuit.
The display panel according to claim 13, wherein, in the second direction, the width of the high potential line is greater than the width of the low potential line.
According to the display panel of claim 13, the second source-drain layer further includes a plurality of clock lines disposed between the low potential line and the high potential line, wherein the plurality of clock lines extend along the first direction and are arranged along the second direction; Some of the multiple clock lines overlap with the output circuit, and some of the multiple clock lines overlap with the receiving circuit.
According to the display panel of claim 15, the plurality of clock lines include a first clock line, a second clock line, a third clock line, and a fourth clock line arranged at intervals, wherein the first clock line overlaps with the output circuit, and the second clock line, the third clock line, and the fourth clock line overlap with the receiving circuit. Each of the gate driving units is connected to two different clock lines among the first, second, third, and fourth clock lines.
The display panel according to claim 15, wherein, in the second direction, the width of one of the clock lines is greater than the width of the low-potential line, and the width of one of the clock lines is less than the width of the high-potential line.
The display panel according to any one of claims 1 to 17, wherein the receiving circuit comprises: The first transistor has its gate connected to a first type of clock line, its drain connected to a low potential line, and its source connected to a second node. The second transistor has its gate connected to a first type of clock line, its drain connected to an initial signal line or the output of the gate driving unit of the previous stage, and its source connected to a third node. The third transistor has its gate connected to a third node, its drain connected to a first-type clock line, and its source connected to a second node. The fourth transistor has its gate connected to a second type of clock line, its drain connected to the source of a fifth transistor, and its source connected to a third node. The fifth transistor has its gate connected to the second node and its drain connected to the high potential line. The eighth transistor has its gate connected to a low potential line, its drain connected to a third node, and its source connected to a first node. The drain of the first output transistor is connected to the second type of clock line.
The display panel according to claim 18, wherein the first gate layer of the display panel includes the gate of the second transistor, the first active layer of the display panel includes the active portion of the second transistor, and the gate of the second transistor extends along a second direction; The active portion of the second transistor includes at least two connected active branches, which are arranged side by side along the second direction, and the gate of the second transistor overlaps with both of the at least two active branches.
A display device, wherein the display device includes a display panel as described in any one of claims 1 to 19.

Description

Display panel and display device Technical Field This application relates to the field of displays, and in particular to a display panel and display device. Background Technology Current OLED (Organic Light-Emitting Diode) display devices face increasingly stringent requirements for power consumption and screen-to-body ratio. To reduce power consumption and increase screen-to-body ratio, Low Temperature Polysilicon Oxide (LTPO) technology is employed. LTPO technology utilizes both low-temperature polysilicon thin-film transistors (LTPS) and oxide thin-film transistors (OTCs), allowing the driving circuit to combine the advantages of both technologies, thereby reducing power consumption and leakage current. Currently, display devices using LTPO technology have a large number of film layers, which in turn requires a large number of photomasks, resulting in a more complex process and higher costs. Summary of the Invention This application provides a display panel and display device to solve the technical problem of complex manufacturing processes in existing display devices using LTPO technology. To address the above issues, the technical solution provided in this application is as follows: This application proposes a display panel including a plurality of gate driving units. Each gate driving unit includes an output circuit, a receiving circuit, and a storage capacitor connected to each other. The output circuit includes a first output transistor and a second output transistor connected to each other. The drain of the first output transistor is connected to a clock line, and the drain of the second output transistor is connected to a high potential line. The area of the first output transistor is larger than the area of the second output transistor. The output circuit and the receiving circuit both include a gate transistor. The active portion of the gate transistor is located in the first active layer. One plate of the storage capacitor is located in the second active layer. The gate of the gate transistor and the other plate of the storage capacitor are located in the first gate layer. The first gate layer, the first active layer, and the second active layer are all disposed in different layers. Attached Figure Description Figure 1 is a simplified diagram of the first structure of the display panel of this application. Figure 2 is an equivalent circuit diagram of the pixel driving circuit in the display panel of this application. Figure 3 is a simplified diagram of the second structure of the display panel of this application. Figure 4 is a simplified diagram of the third structure of the display panel of this application. Figure 5 is an equivalent circuit diagram of the gate driving circuit in the display panel of this application. Figure 6 is a schematic diagram of the film layer in the display panel of this application. Figure 7 is a film layer diagram of the first gate layer in the display panel of this application. Figure 8 is a film diagram of the first active layer in the display panel of this application. Figure 9 is a stacked diagram of the first active layer and the first gate layer in the display panel of this application. Figure 10 is a film diagram of the second active layer in the display panel of this application. Figure 11 is a stacked diagram of the first active layer, the second active layer, and the first gate layer in the display panel of this application. Figure 12 is a film layer diagram of the second gate layer in the display panel of this application. Figure 13 is a stacked diagram of the first active layer, the second active layer, the first gate layer and the second gate layer in the display panel of this application. Figure 14 is a film diagram of the first source and drain layer in the display panel of this application. Figure 15 is a stacked diagram of the first active layer, second active layer, first gate layer, second gate layer and first source/drain layer in the display panel of this application. Figure 16 is a film diagram of the second source and drain layer in the display panel of this application. Figure 17 is a stacked diagram of the first active layer, second active layer, first gate layer, second gate layer, first source-drain layer and second source-drain layer in the display panel of this application. Figure 18 is a connection diagram of four consecutive gate driving units and clock lines in the display panel of this application. Embodiments of the present invention The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific