Search

WO-2026091190-A1 - DISPLAY PANEL

WO2026091190A1WO 2026091190 A1WO2026091190 A1WO 2026091190A1WO-2026091190-A1

Abstract

Disclosed in the present application is a display panel. A gate driving unit of the display panel comprises an output circuit, a receiving circuit and a storage capacitor, which are connected to one another, wherein the output circuit and the receiving circuit each comprise a gate transistor, an active portion of at least one gate transistor is located in a first active layer, one electrode plate of the storage capacitor is located in a second active layer, a gate electrode of the gate transistor and the other electrode plate of the storage capacitor are located in a first gate layer, and the first gate layer, the first active layer and the second active layer are all arranged in different layers.

Inventors

  • ZHANG, YUHENG
  • LIU, HANG

Assignees

  • 武汉华星光电半导体显示技术有限公司

Dates

Publication Date
20260507
Application Date
20241115
Priority Date
20241104

Claims (20)

  1. A display panel includes a plurality of gate driving units, each gate driving unit including an output circuit, a receiving circuit and a storage capacitor connected to each other, the output circuit and the receiving circuit both including gate transistors, and the area of the gate transistor in the output circuit is larger than the area of the gate transistor in the receiving circuit. In this configuration, the active portion of at least one of the gate transistors is located in the first active layer, one plate of the storage capacitor is located in the second active layer, the gate of the gate transistor and the other plate of the storage capacitor are located in the first gate layer, and the first gate layer, the first active layer and the second active layer are all disposed in different layers.
  2. According to claim 1, the display panel, wherein the output circuit includes a first output transistor, the receiving circuit includes a first node control module, and the first output transistor and the first node control module are connected to a first node; The storage capacitor includes a first capacitor, which includes a first plate and a second plate. The first plate and the second plate are respectively connected to different internal nodes in the first node control module. The first plate is located in the second active layer, and the second plate is located in the first gate layer.
  3. According to claim 2, the display panel includes a second output transistor connected to the first output transistor, and the receiving circuit includes a second node control module, wherein the second output transistor and the second node control module are connected to a second node. The storage capacitor includes a second capacitor, which includes a third plate and a fourth plate. The third plate and the fourth plate are respectively connected to different internal nodes in the second node control module. The third plate is located in the second active layer, and the fourth plate is located in the first gate layer.
  4. According to claim 3, the overlapping area of the first electrode plate and the second electrode plate is greater than the overlapping area of the third electrode plate and the fourth electrode plate.
  5. According to claim 3, the display panel further includes a third capacitor, the third capacitor including a fifth plate and a sixth plate, the fifth plate being located in the second active layer and the sixth plate being located in the first gate layer; The sixth electrode plate is connected to the source of the second output transistor, and the fifth electrode plate is connected to the second node.
  6. According to claim 5, the display panel, wherein the first gate layer includes a first gate of the first output transistor and a second gate of the second output transistor, and the first gate and the second gate are arranged in a first direction; The area of the first gate is smaller than the area of the second gate.
  7. According to the display panel of claim 6, the first gate includes a first main gate and a plurality of first branch gates connected to the first main gate, the first main gate extends along the first direction, the plurality of first branch gates extend along the second direction, and the plurality of first branch gates are spaced apart in the first direction. The second gate includes a second main gate and a plurality of second branch gates connected to the second main gate. The second main gate extends along the first direction, the plurality of second branch gates extend along the second direction, and the plurality of second branch gates are spaced apart in the first direction. The second main gate and part of the second branch gate are multiplexed as the sixth electrode plate. The second direction is parallel to the scan line of the display panel. The angle between the first direction and the second direction is greater than 0° and less than or equal to 90°.
  8. According to claim 7, in the second direction, the linewidth of the first main gate is smaller than the linewidth of the second main gate.
  9. The display panel according to claim 7, wherein, in the second direction, the length of the first branch gate is less than the length of the second branch gate.
  10. According to the display panel of claim 7, the first gate layer further includes a second electrode plate of the first capacitor and a fourth electrode plate of the second capacitor, the second electrode plate and the fourth electrode plate are arranged along the first direction, and the fourth electrode plate and the sixth electrode plate are arranged along the second direction; The second electrode plate extends along the second direction and is connected to the first main gate.
  11. According to the display panel of claim 10, the second active layer includes a first electrode plate of the first capacitor, a third electrode plate of the second capacitor, and a fifth electrode plate of the third capacitor. Wherein, a portion of the outer contour of the first electrode plate is wider than the outer contour of the second electrode plate, a portion of the outer contour of the third electrode plate is wider than the outer contour of the fourth electrode plate, and a portion of the outer contour of the fifth electrode plate is wider than the outer contour of the sixth electrode plate.
  12. According to claim 7, the display panel further includes a first source-drain layer disposed on the side of the second active layer away from the first active layer, the first source-drain layer including a first source and a first drain of the first output transistor; The first drain includes a plurality of first branch drains, the first source includes a plurality of first branch sources, the plurality of first branch drains and the plurality of first branch sources extend along the second direction, and the plurality of first branch drains and the plurality of first branch sources are arranged at intervals along the first direction. Each of the first branch gates has a first branch drain and a first branch source on both sides of the first direction.
  13. The display panel according to claim 12, wherein the first source-drain layer further includes a second source and a second drain of the second output transistor; The second drain includes a plurality of second branch drains, the second source includes a plurality of second branch sources, the plurality of second branch drains and the plurality of second branch drains extend along the second direction, and the plurality of second branch drains and the plurality of second branch sources are arranged at intervals along the first direction, and each second branch gate is provided with a second branch drain and a second branch source on both sides of the first direction. The first source-drain layer further includes a drain backbone extending along the first direction, a plurality of second branch drains connected to the drain backbone, and a plurality of second branch sources, a plurality of first branch drains and a plurality of first branch sources separately disposed from the drain backbone.
  14. The display panel according to claim 13, wherein the display panel further comprises a second gate layer disposed between the second active layer and the first source-drain layer, the second gate layer comprising an output trace extending along the first direction; In this configuration, the ends of the plurality of first branch sources and the plurality of second branch sources that are furthest from the receiving circuit pass through vias and are electrically connected to the output traces.
  15. According to the display panel of claim 14, a plurality of second branch drains and a plurality of second branch sources are staggered along the first direction, and the ends of the plurality of second branch drains near the receiving circuit are connected to the drain trunk, while the ends of the plurality of second branch drains away from the receiving circuit are separated from the output trace.
  16. According to the display panel of claim 13, the first source-drain layer further includes a first low-potential line, a first clock line, and a second clock line connected to the output circuit. The first low-potential line, the first clock line, and the second clock line are disposed at the end of the receiving circuit away from the output circuit. The first low-potential line, the first clock line, and the second clock line all extend along the first direction and are arranged along the second direction. The first low-potential line is positioned close to the receiving circuit, while the second clock line is positioned away from the receiving circuit. The first clock line is located between the first low-potential line and the second clock line.
  17. According to the display panel of claim 13, the display panel further includes a second source-drain layer disposed on the side of the first source-drain layer away from the first active layer, the second source-drain layer including a second low-potential line and a first high-potential line, the second low-potential line and the first high-potential line both extending along the first direction and arranged along the second direction; Wherein, the second low potential line overlaps with a plurality of first branch gates and a plurality of second branch gates, and the second low potential line passes through a first connection hole and is connected to a plurality of first branch drains; The first high-potential line overlaps with the drain main body and part of the receiving circuit, and the first high-potential line passes through the second connection hole and is connected to the drain main body.
  18. The display panel according to claim 17, wherein, in the second direction, the width of the first low-potential line is smaller than the width of the second low-potential line.
  19. The display panel according to claim 17, wherein, in the second direction, the width of the first high-potential line is greater than the width of the second low-potential line.
  20. The display panel according to claim 17, wherein the diameter of the first connecting hole is smaller than the diameter of the second connecting hole.

Description

Display panel Technical Field This application relates to the field of displays, and more particularly to a display panel. Background Technology Current OLED (Organic Light-Emitting Diode) display devices face increasingly stringent requirements for power consumption and screen-to-body ratio. To reduce power consumption and increase screen-to-body ratio, Low Temperature Polysilicon Oxide (LTPO) technology is employed. LTPO technology utilizes both low-temperature polysilicon thin-film transistors (LTPS) and oxide thin-film transistors (OTCs), allowing the driving circuit to combine the advantages of both technologies, thereby reducing power consumption and leakage current. Currently, display devices using LTPO technology have a large number of film layers, which in turn requires a large number of photomasks, resulting in a more complex process and higher costs. Summary of the Invention This application provides a display panel to solve the technical problem of complex manufacturing processes in existing display devices using LTPO technology. To address the above issues, the technical solution provided in this application is as follows: This application proposes a display panel including a plurality of gate driving units; each gate driving unit includes an output circuit, a receiving circuit and a storage capacitor connected to each other, both the output circuit and the receiving circuit include gate transistors, and the area of the gate transistor in the output circuit is larger than the area of the gate transistor in the receiving circuit. In this configuration, the active portion of at least one of the gate transistors is located in the first active layer, one plate of the storage capacitor is located in the second active layer, the gate of the gate transistor and the other plate of the storage capacitor are located in the first gate layer, the first gate layer is disposed between the first active layer and the second active layer, and the materials of the first active layer and the second active layer are different. Attached Figure Description Figure 1 is a simplified diagram of the first structure of the display panel of this application; Figure 2 is an equivalent circuit diagram of the pixel driving circuit in the display panel of this application; Figure 3 is a simplified diagram of the second structure of the display panel of this application; Figure 4 is a simplified diagram of the third structure of the display panel of this application; Figure 5 is an equivalent circuit diagram of the gate driving circuit in the display panel of this application; Figure 6 is a schematic diagram of the film layer in the display panel of this application; Figure 7 is a film layer diagram of the first gate layer in the display panel of this application. Figure 8 is a film layer diagram of the first active layer in the display panel of this application. Figure 9 is a stacked diagram of the first active layer and the first gate layer in the display panel of this application. Figure 10 is a film diagram of the second active layer in the display panel of this application. Figure 11 is a stacked diagram of the first active layer, the second active layer, and the first gate layer in the display panel of this application. Figure 12 is a film layer diagram of the second gate layer in the display panel of this application. Figure 13 is a stacked diagram of the first active layer, the second active layer, the first gate layer and the second gate layer in the display panel of this application. Figure 14 is a film diagram of the first source and drain layer in the display panel of this application. Figure 15 is a stacked diagram of the first active layer, second active layer, first gate layer, second gate layer and first source/drain layer in the display panel of this application. Figure 16 is a film diagram of the second source/drain layer in the display panel of this application. Figure 17 is a stacked diagram of the first active layer, second active layer, first gate layer, second gate layer, first source-drain layer and second source-drain layer in the display panel of this application. Embodiments of the present invention The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In the description of this application, it should be understood that the terms "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "top",