WO-2026091330-A1 - ARRAY SUBSTRATE AND METHOD FOR PREPARING SAME, DISPLAY PANEL, AND DISPLAY DEVICE

WO2026091330A1WO 2026091330 A1WO2026091330 A1WO 2026091330A1WO-2026091330-A1

Abstract

The present application provides an array substrate and a method for preparing same, a display panel, and a display device. The array substrate comprises a substrate, an active layer, a first driving transistor and a first switching transistor, wherein the active layer is disposed on one side of the substrate; a control terminal of the first driving transistor is electrically connected to a first node; a first electrode of the first switching transistor is electrically connected to a second electrode of the first driving transistor, and a second electrode of the first switching transistor is electrically connected to the first node; and the first switching transistor comprises a first sub-switching transistor and a second sub-switching transistor. The first sub-switching transistor comprises a first channel portion located in the active layer, and the second sub-switching transistor comprises a second channel portion located in the active layer, wherein a gap is present between the orthographic projection of the first channel portion on the substrate and the orthographic projection of the second channel portion on the substrate, and the electrical resistivity of the first channel portion is less than the electrical resistivity of the second channel portion.

Inventors

ZHENG, YING
YU, YUN
YI, Shijuan

Assignees

武汉天马微电子有限公司

Dates

Publication Date: 20260507
Application Date: 20250210
Priority Date: 20241031

Claims (18)

An array substrate, comprising: Substrate; An active layer is disposed on one side of the substrate; A first driving transistor, the control terminal of the first driving transistor is electrically connected to a first node; A first switching transistor, wherein a first terminal of the first switching transistor is electrically connected to a second terminal of the first driving transistor, and the second terminal of the first switching transistor is electrically connected to the first node, and the first switching transistor includes a first sub-switching transistor and a second sub-switching transistor. The first sub-switch transistor includes a first channel portion located within the active layer, and the second sub-switch transistor includes a second channel portion located within the active layer. The first channel portion is electrically connected to the second terminal of the first switch transistor, and the second channel portion is electrically connected to the first terminal of the first switch transistor. There is a gap between the orthographic projection of the first channel portion on the substrate and the orthographic projection of the second channel portion on the substrate. The resistivity of the first channel is less than that of the second channel.
According to claim 1, the doping concentration in the first channel portion is greater than the doping concentration in the second channel portion.
According to claim 2, the array substrate is characterized in that the doping concentration of the first channel is E, and E satisfies: 10¹² particles/cm⁻³ ≤ E ≤ 10¹⁵ particles/cm⁻³.
According to the array substrate of claim 2, the ratio between the doping concentration in the first channel portion and the doping concentration in the second channel portion is a, where a satisfies: 3≤a≤200.
According to claim 1, the array substrate is characterized in that the first channel portion is subjected to plasma treatment.
According to the array substrate of claim 1, the control terminal of the first driving transistor includes a third channel portion located within the active layer, wherein the resistivity of the first channel portion is less than the resistivity of the third channel portion.
The array substrate according to claim 1 further includes a second switching transistor, the first electrode of the second switching transistor being electrically connected to the first node, and the control terminal of the second switching transistor including a third sub-switching transistor and a fourth sub-switching transistor. The third sub-switch transistor includes a fourth channel portion located within the active layer, the fourth sub-switch transistor includes a fifth channel portion located within the active layer, the fourth channel portion is electrically connected to a first terminal of the second switch transistor, the fifth channel portion is electrically connected to a second terminal of the second switch transistor, and there is a gap between the orthographic projection of the fourth channel portion on the substrate and the orthographic projection of the fifth channel portion on the substrate. The resistivity of the fourth channel is less than that of the fifth channel.
According to the array substrate of claim 1, the active layer further includes a first active structure, the two ends of the first active structure being respectively connected to the first channel portion and the second channel portion; The array substrate further includes a shielding structure located on one side of the active layer in the thickness direction of the substrate. The orthographic projection of the shielding structure on the substrate overlaps with the orthographic projection of the first active structure on the substrate, and the shielding structure is used to transmit a constant voltage potential.
The array substrate according to claim 8 further includes a storage capacitor, the storage capacitor including a first electrode plate located within the first conductive layer and a second electrode plate located on the side of the first electrode plate opposite to the substrate, and the control terminal of the first switching transistor is located within the first conductive layer. The second electrode plate includes the shielding structure.
According to claim 9, the array substrate wherein the orthographic projection of the second electrode on the substrate covers the orthographic projection of the first active structure on the substrate.
The array substrate according to claim 8 further includes a second conductive layer located on the side of the active layer facing the substrate, and a shielding structure is located within the second conductive layer.
According to the array substrate of claim 8, the aspect ratio of the first active structure is greater than the aspect ratio of at least one of the first channel portion and the second channel portion.
According to claim 1, the array substrate wherein the active layer is made of low-temperature polycrystalline silicon.
A display panel includes an array substrate as described in any one of claims 1 to 13 and a plurality of sub-pixels, the array substrate including a plurality of pixel circuits, the pixel circuits including a first driving transistor and a first switching transistor, the pixel circuits being used to control the light emission of the sub-pixels.
The display panel according to claim 14, wherein the plurality of sub-pixels includes a first sub-pixel and a second sub-pixel with different colors, and the plurality of pixel circuits includes a first pixel circuit for driving the first sub-pixel and a second pixel circuit for driving the second sub-pixel. Wherein, the resistivity of the first switching transistor in the first pixel circuit corresponding to the first channel portion is less than the resistivity of the first switching transistor in the second pixel circuit corresponding to the first channel portion.
The display panel according to claim 15, wherein the first sub-pixel is used to emit green light.
A display device comprising a display panel as described in any one of claims 14 to 16.
A method for fabricating an array substrate, the array substrate including a first switching transistor and a first driving transistor, wherein the control terminal of the first driving transistor is electrically connected to a first node, the first electrode of the first switching transistor is electrically connected to the second electrode of the first driving transistor, the second electrode of the first switching transistor is electrically connected to the first node, and the first switching transistor includes a first sub-switching transistor and a second sub-switching transistor; the fabrication method includes: An active layer is formed on one side of the substrate, the first sub-switch transistor includes a first channel portion located within the active layer, and the second sub-switch transistor includes a second channel portion located within the active layer; The first channel portion is subjected to plasma treatment to make the resistivity of the first channel portion less than that of the second channel portion.

Description

Array substrate and its fabrication method, display panel, display device Cross-reference of related applications This application claims priority to Chinese Patent Application No. 202411541523.7, filed on October 31, 2024, entitled “Array substrate and method of preparation thereof, display panel, display device”, the entire contents of which are incorporated herein by reference. Technical Field This application relates to the field of display device technology, and in particular to an array substrate and its preparation method, a display panel, and a display device. Background Technology With the continuous development of display technologies such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED), display panels are widely used in various industries. However, during the use of current display panels, screen flickering may still occur, affecting the user's viewing experience. Summary of the Invention This application provides an array substrate and its fabrication method, a display panel, and a display device, which can improve screen flickering issues. In a first aspect, embodiments of this application provide an array substrate, which includes a substrate, an active layer, a first driving transistor, and a first switching transistor. The active layer is disposed on one side of the substrate. The control terminal of the first driving transistor is electrically connected to a first node. The first electrode of the first switching transistor is electrically connected to the second electrode of the first driving transistor. The second electrode of the first switching transistor is electrically connected to the first node. The first switching transistor includes a first sub-switching transistor and a second sub-switching transistor. The first sub-switch transistor includes a first channel portion located within the active layer, and the second sub-switch transistor includes a second channel portion located within the active layer. The first channel portion is electrically connected to the second terminal of the first switch transistor, and the second communication portion is electrically connected to the first terminal of the first switch transistor. There is a gap between the orthographic projection of the first channel portion onto the substrate and the orthographic projection of the second channel portion onto the substrate. The resistivity of the first channel portion is less than the resistivity of the second channel portion. Secondly, embodiments of this application provide a display panel, which includes an array substrate as described in any of the foregoing embodiments and a plurality of sub-pixels. The array substrate includes a plurality of pixel circuits, and the pixel circuits include a first driving transistor and a first switching transistor. The pixel circuits are used to control the light emission of the sub-pixels. Thirdly, embodiments of this application provide a display device, which includes the display panel in any of the foregoing embodiments. Fourthly, embodiments of this application provide a method for fabricating an array substrate. The array substrate includes a first switching transistor and a first driving transistor. The control terminal of the first driving transistor is electrically connected to a first node. The first electrode of the first switching transistor is electrically connected to the second electrode of the first driving transistor. The second electrode of the first switching transistor is electrically connected to the first node. The first switching transistor includes a first sub-switching transistor and a second sub-switching transistor. The fabrication method includes: An active layer is formed on one side of the substrate; The first channel section is subjected to plasma treatment. This application provides an array substrate and its fabrication method, a display panel, and a display device. Since the first channel portion is located between the first node and the fifth node and the first channel portion has strong conductivity, when there is a certain voltage difference between the fifth node and the first node, the current can flow from the fifth node to the first node quickly through the first channel portion. This allows the potential at the first node to be consistent with the potential at the fifth node in a short time, thereby reducing the leakage between the first node and the fifth node during the light-emitting stage, reducing the flicker of the displayed image, and improving the display effect. Attached Figure Description To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Figure 1 is a top view of a partial film layer in an array substrate provided in an embodiment of this appli