WO-2026091357-A1 - SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR

WO2026091357A1WO 2026091357 A1WO2026091357 A1WO 2026091357A1WO-2026091357-A1

Abstract

Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, comprising a device layer, buried power rails, and through-silicon vias, wherein the through-silicon vias are connected to the device layer by means of the buried power rails; a power supply network layer disposed on the substrate, wherein the power supply network layer comprises at least one layer of first power supply arrays and at least one layer of second power supply arrays, and the first power supply arrays are connected to the buried power rails by means of the through-silicon vias; and capacitor structures disposed between the first power supply arrays and the second power supply arrays, and respectively connected to the first power supply arrays and the second power supply arrays by means of lower electrodes and upper electrodes of the capacitor structures.

Inventors

CHEN, JUN
LIN, LIEN-KUAN
LEE, TZUNG-HAN
WANG, Chunyang

Assignees

长鑫科技集团股份有限公司

Dates

Publication Date: 20260507
Application Date: 20250305
Priority Date: 20241030

Claims (15)

A semiconductor structure, characterized in that it comprises: The substrate (101) includes a device layer (103), a buried power rail (BPR), and a through silicon via (102), wherein the through silicon via (102) is connected to the device layer (103) through the buried power rail (BPR); A power network layer (104) is disposed on the substrate (101). The power network layer (104) includes at least one first power array (1041) and at least one second power array (1042). The first power array (1041) is connected to the buried power rail (BPR) through the through silicon via (102). A capacitor structure (108) is disposed between the first power array (1041) and the second power array (1042), and is connected to the first power array (1041) and the second power array (1042) respectively through the lower electrode (1081) and the upper electrode (1084) of the capacitor structure (108).
The semiconductor structure according to claim 1 is characterized in that the first power supply array (1041) extends along a first direction (Y), the second power supply array (1042) extends along a second direction (X), the first direction (Y) and the second direction (X) intersect in a direction parallel to the substrate (101), and the projections of the first power supply array (1041) and the second power supply array (1042) in a direction perpendicular to the substrate (101) have overlapping portions.
According to claim 2, the semiconductor structure is characterized in that the first power array (1041) and the second power array (1042) each include at least two power lines (Vdd) and at least two ground lines (Vss), the at least two power lines (Vdd) and at least two ground lines (Vss) of the first power array (1041) are parallel to each other and staggered along the second direction (X), and the at least two power lines (Vdd) and at least two ground lines (Vss) of the second power array (1042) are parallel to each other and staggered along the first direction (Y).
According to the semiconductor structure of claim 3, the overlapping portion of the projection of the first power array (1041) and the second power array (1042) in a direction perpendicular to the substrate (101) includes at least one first region (I) and at least one second region (II), wherein the first region (I) is the overlapping portion of the projection of the power line (Vdd) of the first power array (1041) and the power line (Vdd) of the second power array (1042) in a direction perpendicular to the substrate (101) and the overlapping portion of the projection of the ground line (Vss) of the first power array (1041) and the ground line (Vss) of the second power array (1042) in a direction perpendicular to the substrate (101); The second region (II) is the portion where the projection of the ground line (Vss) of the first power array (1041) and the power line (Vdd) of the second power array (1042) overlaps in a direction perpendicular to the substrate (101), and the portion where the projection of the power line (Vdd) of the first power array (1041) and the ground line (Vss) of the second power array (1042) overlaps in a direction perpendicular to the substrate (101).
According to the semiconductor structure of claim 4, a contact plug (CT) is further provided between the first power array (1041) and the second power array (1042), the contact plug (CT) being disposed in the first region (I) for connecting the power line (Vdd) of the first power array (1041) to the power line (Vdd) of the second power array (1042) or connecting the ground line (Vss) of the first power array (1041) to the ground line (Vss) of the second power array (1042).
According to claim 4, the semiconductor structure is characterized in that the capacitor structure (108) is disposed in the second region (II), the lower electrode (1081) of the capacitor structure (108) is connected to the power line (Vdd) of the first power array (1041), and the upper electrode (1084) of the capacitor structure (108) is connected to the ground line (Vss) of the second power array (1042); or, the lower electrode (1081) of the capacitor structure (108) is connected to the ground line (Vss) of the first power array (1041), and the upper electrode (1084) of the capacitor structure (108) is connected to the power line (Vdd) of the second power array (1042).
According to the semiconductor structure of claim 3, the first power array (1041) has the same number of power lines (Vdd) and ground lines (Vss), and the second power array (1042) has the same number of power lines (Vdd) and ground lines (Vss).
According to the semiconductor structure of claim 7, the spacing between adjacent power lines (Vdd) and ground lines (Vss) is in the range of 0.1-1.5 μm.
A method for fabricating a semiconductor structure, characterized by comprising: A substrate (101) is provided, wherein a device layer (103), a buried power rail (BPR) and a through silicon via (102) are formed therein, and the through silicon via (102) is connected to the device layer (103) through the buried power rail (BPR). A power network layer (104) and a capacitor structure (108) are formed on the substrate (101). The power network layer (104) includes at least one first power array (1041) and at least one second power array (1042). The first power array (1041) is connected to the buried power rail (BPR) through the through silicon via (102). The capacitor structure (108) is formed between the first power array (1041) and the second power array (1042) and is connected to the first power array (1041) and the second power array (1042) through the lower electrode (1081) and the upper electrode (1084) of the capacitor structure (108), respectively.
According to the preparation method of claim 9, the step of forming the power network layer (104) and the capacitor structure (108) on the substrate (101) includes: The substrate (101) has a first surface (S1) and a second surface (S2). An isolation layer (105) is formed on the first surface (S1) of the substrate (101). A first power array (1041) is formed within the patterned isolation layer (105). The first power array (1041) extends along a first direction (Y) and includes at least two power lines (Vdd) and at least two ground lines (Vss). An insulating layer (106) is deposited on the isolation layer (105) and the first power array (1041), and the insulating layer (106) is patterned. The patterned insulating layer (106) exposes part of the power line (Vdd) and the ground line (Vss) of the first power array (1041). Within the patterned insulating layer (106), the capacitor structure (108), the contact plug (CT), and the second power array (1042) are sequentially formed. The second power array (1042) extends along a second direction (X) and includes at least two power lines (Vdd) and at least two ground lines (Vss). The first direction (Y) and the second direction (X) intersect in a direction parallel to the substrate (101). The projection portions of the first power array (1041) and the second power array (1042) in a direction perpendicular to the substrate (101) coincide. The contact plug (CT) and the capacitor structure (108) are connected between the first power array (1041) and the second power array (1042).
According to the preparation method of claim 10, the lower electrode (1081) of the capacitor structure (108) is connected to the power line (Vdd) of the first power array (1041), and the upper electrode (1084) of the capacitor structure (108) is connected to the ground line (Vss) of the second power array (1042); or, the lower electrode (1081) of the capacitor structure (108) is connected to the ground line (Vss) of the first power array (1041), and the upper electrode (1084) of the capacitor structure (108) is connected to the power line (Vdd) of the second power array (1042).
According to the preparation method of claim 10, the contact plug (CT) is used to connect the power line (Vdd) of the first power array (1041) to the power line (Vdd) of the second power array (1042), or to connect the ground line (Vss) of the first power array (1041) to the ground line (Vss) of the second power array (1042).
According to the preparation method of claim 10, the insulating layer (106) comprises a first barrier layer (1061), a first insulating layer (1062), a second barrier layer, and a second insulating layer, wherein the capacitor structure (108), the contact plug (CT), and the second power array (1042) are sequentially formed within the patterned insulating layer (106), comprising: The first barrier layer (1061) and the first insulating layer (1062) are deposited and patterned to form a first trench (107) that exposes a portion of the power line (Vdd) or the ground line (Vss) of the first power array (1041). The lower electrode (1081), dielectric layer (1082), barrier layer (1083) and upper electrode (1084) are sequentially deposited in the first trench (107). The lower electrode (1081), dielectric layer (1082), barrier layer (1083) and upper electrode (1084) constitute the capacitor structure (108). The lower electrode (1081) is connected to the power line (Vdd) or ground line (Vss) of the first power array (1041). The second barrier layer (1063) and the second insulating layer (1064) are deposited and formed. The first barrier layer (1061), the first insulating layer (1062), the second barrier layer (1063) and the second insulating layer (1064) are patterned to form a second trench (109). The second trench (109) exposes a portion of the power line (Vdd) or the ground line (Vss) of the first power array (1041) and the upper electrode (1084) of the capacitor structure (108). Conductive material is deposited in the second trench (109) to form the contact plug (CT) and the second power array (1042).
According to the fabrication method of claim 10, the device layer (103), the buried power rail (BPR), and the through-silicon via (102) are formed within the substrate (101), comprising: The through-silicon via (102) is formed in the substrate (101), and the through-silicon via (102) penetrates the first surface (S1) and the second surface (S2) of the substrate (101); The buried power rail (BPR) and the device layer (103) are sequentially formed on the second surface (S2) of the substrate (101).
The fabrication method according to claim 14 is characterized in that, after forming the device layer (103) in the substrate (101), a signal interconnect layer (SL) is further formed on the device layer (103).

Description

Semiconductor structure and its preparation method Cross-referencing This disclosure claims priority to Chinese Patent Application No. 202411538521.2, filed on October 30, 2024, entitled "Semiconductor Structure and Preparation Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method. Background Technology In traditional chip manufacturing and advanced 2.5D or 3D packaging, wiring is typically done on the front side of the wafer, with signal lines and power lines vertically stacked and connected to form active electronic components (Semiconductor devices) with multilayer metal interconnect structures. This method results in both signal interconnect networks and power supply networks on the front side of the chip, making it difficult to further reduce the overall package size. Based on this, a back-side power supply network (BSPDN) chip structure was proposed to overcome the shortcomings of the front-side power supply structure. However, this introduces new problems, such as voltage drop due to power conduction path limitations, leading to higher chip power consumption. Therefore, how to further optimize the chip structure and shorten the power conduction path based on back-side power supply technology to improve device performance has become an urgent problem to be solved. Summary of the Invention According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: The substrate includes a device layer, a buried power rail, and a through-silicon via (TSV), wherein the TSV is connected to the device layer through the buried power rail. A power network layer is disposed on the substrate, the power network layer including at least one first power array and at least one second power array, the first power array being connected to the buried power rail through the through silicon via; A capacitor structure is disposed between the first power array and the second power array, and is connected to the first power array and the second power array respectively through the lower electrode and the upper electrode of the capacitor structure. In some embodiments, the first power array extends along a first direction, the second power array extends along a second direction, the first direction and the second direction intersect in a direction parallel to the substrate, and the projections of the first power array and the second power array in a direction perpendicular to the substrate have overlapping portions. In some embodiments, both the first power array and the second power array include at least two power lines and at least two ground lines. The at least two power lines and at least two ground lines of the first power array are parallel to each other and staggered along the second direction, and the at least two power lines and at least two ground lines of the second power array are parallel to each other and staggered along the first direction. In some embodiments, the projected overlap of the first power array and the second power array in a direction perpendicular to the substrate includes at least one first region and at least one second region. The first region is the projected overlap of the power lines of the first power array and the power lines of the second power array in a direction perpendicular to the substrate, and the projected overlap of the ground lines of the first power array and the ground lines of the second power array in a direction perpendicular to the substrate. The second region is the projected overlap of the ground lines of the first power array and the power lines of the second power array in a direction perpendicular to the substrate, and the projected overlap of the power lines of the first power array and the ground lines of the second power array in a direction perpendicular to the substrate. In some embodiments, a contact plug is further provided between the first power array and the second power array. The contact plug is disposed in the first region and is used to connect the power line of the first power array to the power line of the second power array or to connect the ground line of the first power array to the ground line of the second power array. In some embodiments, the capacitor structure is disposed in the second region, the lower electrode of the capacitor structure is connected to the power line of the first power array, and the upper electrode of the capacitor structure is connected to the ground line of the second power array; or, the lower electrode of the capacitor structure is connected to the ground line of the first power array, and the upper electrode of the capacitor structure is connected to the power line of the second power array. In some embodiments, the number of power lines and ground lines in the first power array is the same,