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WO-2026091369-A1 - SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR

WO2026091369A1WO 2026091369 A1WO2026091369 A1WO 2026091369A1WO-2026091369-A1

Abstract

A semiconductor structure and a method for forming same. The semiconductor structure may at least comprise: a substrate; bit line structures located on the substrate, the plurality of bit line structures extending in a first direction and being arranged at intervals in a second direction, and the first direction being perpendicular to the second direction; first dielectric layers located between respective adjacent bit line structures and arranged at intervals in the first direction; contact structures located between respective adjacent bit line structures, each contact structure being spaced apart from a first dielectric layer; and conductive structures located above the contact structures, the top of each conductive structure being flush with the top of a first dielectric layer. The size of each contact structure gradually decreases from the top of the contact structure to the surface of the substrate in a direction perpendicular to the substrate.

Inventors

  • ZHU, Shun
  • CHEN, Longyang
  • SHI, Luan
  • FANG, Ke
  • CHEN, Yinchu
  • SUN, YAO
  • LI, Guangcheng

Assignees

  • 长鑫科技集团股份有限公司

Dates

Publication Date
20260507
Application Date
20250313
Priority Date
20241030

Claims (17)

  1. A semiconductor structure, characterized in that it comprises: Base (10); Bit line structures (20) are located on the substrate (10). Multiple bit line structures (20) extend along a first direction (X) and are spaced apart along a second direction (Y). The first direction (X) is perpendicular to the second direction (Y). A first dielectric layer (60) is located between adjacent bit line structures (20) and spaced apart along the first direction (X); A contact structure (70) is located between adjacent bit line structures (20), and the contact structure (70) is spaced apart from the first dielectric layer (60); A conductive structure (80) is located above the contact structure (70), and the top of the conductive structure (80) is flush with the top of the first dielectric layer (60). The dimensions of the contact structure (70) gradually decrease from the top of the contact structure (70) to the surface of the substrate (10) along a direction perpendicular to the substrate (10).
  2. According to claim 1, the semiconductor structure is characterized in that the conductive structure (80) includes a first conductive structure (801) and a second conductive structure (802), the first conductive structure (801) is flush with the top surface of the first dielectric layer (60), the second conductive structure (802) is located between the first conductive structure (801) and the contact structure (70), and the conductive structure (80) gradually increases in size from top to bottom along a direction perpendicular to the substrate (10).
  3. According to claim 1, the semiconductor structure is characterized in that the contact area between the conductive structure (80) and the contact structure (70) is greater than the cross-sectional area of the conductive structure (80) at any position, and is also greater than the cross-sectional area of the contact structure (70) at any position.
  4. The semiconductor structure according to claim 1 is characterized in that it further includes a top conductive structure (803), the top conductive structure (803) being located above the conductive structure (80) and covering a portion of the top surface of the first dielectric layer (60).
  5. According to claim 1, the semiconductor structure is characterized in that the size of the first dielectric layer (60) decreases from top to bottom and then increases, and the first dielectric layer (60) also has an air gap (90) which is lower than the interface between the conductive structure (80) and the contact structure (70).
  6. According to claim 1, the semiconductor structure is characterized in that the contact structure (70) includes a first contact structure (701) and a second contact structure (702), the first contact structure (701) is embedded in the substrate (10), the second contact structure (702) is located above the first contact structure (701), and the second contact structure (702) gradually decreases in size from top to bottom along a direction perpendicular to the substrate (10).
  7. A method for forming a semiconductor structure, characterized in that it includes: Provide a base (10); Bit line structures (20) are formed on the substrate (10), the bit line structures (20) extend along a first direction (X) and are spaced apart along a second direction (Y), the first direction (X) is perpendicular to the second direction (Y), and a first opening (301) is provided between adjacent bit line structures (20); A first conductive layer (401) is formed in the first opening (301); The first conductive layer (401) is etched along a third direction (Z) to form a second opening (302), and the remaining first conductive layer (401) serves as the second conductive layer (402). The second conductive layer (402) and the second opening (302) are spaced apart along the first direction (X), and the third direction (Z) is perpendicular to the substrate (10). The second opening (302) is filled with a first dielectric layer (60); The second conductive layer (402) is etched back to form a third opening (303), and the remaining second conductive layer (402) serves as a contact structure (70). A conductive structure (80) is formed in the third opening (303), the conductive structure (80) being located above the contact structure (70); The dimensions of the contact structure (70) gradually decrease from the top of the contact structure (70) to the surface of the substrate (10) along a direction perpendicular to the substrate (10).
  8. The method for forming a semiconductor structure according to claim 7 is characterized in that the conductive structure (80) includes a first conductive structure (801) and a second conductive structure (802), the first conductive structure (801) is located in the third opening (303) and is flush with the top surface of the first dielectric layer (60), the second conductive structure (802) is located between the first conductive structure (801) and the contact structure (70), and the conductive structure (80) gradually increases in size from top to bottom along a direction perpendicular to the substrate (10).
  9. The method for forming a semiconductor structure according to claim 7 is characterized in that the contact area between the conductive structure (80) and the contact structure (70) is greater than the cross-sectional area of the conductive structure (80) at any position and greater than the cross-sectional area of the contact structure (70) at any position.
  10. The method for forming a semiconductor structure according to claim 7 is characterized in that it further includes a top conductive structure (803), which is formed above the conductive structure (80) and covers a portion of the top surface of the first dielectric layer (60).
  11. The method for forming a semiconductor structure according to claim 7 is characterized in that the size of the first dielectric layer (60) decreases and then increases from top to bottom; the first dielectric layer (60) also has an air gap (90), the air gap (90) being lower than the interface between the conductive structure (80) and the contact structure (70).
  12. The method for forming a semiconductor structure according to any one of claims 7-11 is characterized in that the size of the second conductive layer (402) increases first and then decreases from top to bottom, and the method for forming the second conductive layer (402) includes: performing an oxidation process, an etching process and a deoxidation process in a cycle.
  13. The method for forming a semiconductor structure according to claim 12 is characterized in that oxygen is used in the oxidation process, the bias voltage of the oxidation process is gradually increased, and the flow rate of the oxygen is gradually increased; the etching gas in the etching process is chlorine and/or hydrogen bromide gas, the regulating gas in the etching process is oxygen, the flow rate of the etching gas remains constant, and the flow rate of the regulating gas first increases and then decreases; the deoxidation process removes the byproducts generated during the etching process using plasma, and the bias voltage of the deoxidation process is gradually increased.
  14. The method for forming a semiconductor structure according to claim 7 is characterized in that, before forming the first conductive layer (401), the method further includes etching the substrate (10) along the first opening (301) to form a first initial opening (301'), wherein the first conductive layer (401) also fills the first initial opening (301').
  15. The method for forming a semiconductor structure according to claim 14 is characterized in that the contact structure (70) includes a first contact structure (701) and a second contact structure (702), the first contact structure (701) is located at the first initial opening (301'), the second contact structure (702) is located above the first contact structure (701), and the second contact structure (702) gradually decreases in size from top to bottom along a direction perpendicular to the substrate (10).
  16. The method for forming a semiconductor structure according to claim 7 is characterized in that, before etching the first conductive layer (401) along the third direction (Z) to form the second opening (302), it further includes: forming a stacked film layer (50) on the first conductive layer (401), etching the stacked film layer (50) to form a second initial opening (302'), and etching the first conductive layer (401) along the second initial opening (302') to form the second opening (302).
  17. The method for forming a semiconductor structure according to claim 7, characterized in that filling the second opening (302) with the first dielectric layer (60) specifically includes: A first initial dielectric layer (601) is filled into the second opening (302), the first initial dielectric layer (601) also covers the surface of the second conductive layer (402), the first initial dielectric layer (601) is etched back to form a fourth opening (304), a second initial dielectric layer (602) is formed in the fourth opening (304), the first initial dielectric layer (601) and the second initial dielectric layer (602) together constitute the first dielectric layer (60).

Description

A semiconductor structure and its manufacturing method Cross-referencing This application claims priority to Chinese Patent Application No. 202411538538.8, filed on October 30, 2024, entitled “A Semiconductor Structure and a Method for Manufacturing the Same”, the entire contents of which are incorporated herein by reference. Technical Field This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology In the manufacturing process of DRAM (Dynamic Random Access Memory), as chip size continues to shrink, the challenges in the process become increasingly significant, which may lead to poor connection performance of conductive and contact structures, short circuits between adjacent conductive structures or adjacent contact structures, and other problems. Summary of the Invention This disclosure provides a semiconductor structure and its manufacturing method, which at least helps to solve the problems of deterioration of pad structure and contact nodes, and short circuits between different conductive structures. According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: Base; Bit line structure, located on the substrate, multiple bit line structures extend along a first direction and are spaced apart along a second direction, the first direction being perpendicular to the second direction; A first dielectric layer is located between adjacent bit line structures and is spaced apart along a first direction; A contact structure is located between adjacent bit line structures, and the contact structure is spaced apart from the first dielectric layer; A conductive structure is located above the contact structure, and the top of the conductive structure is flush with the top of the first dielectric layer. The dimensions of the contact structure gradually decrease from the top of the contact structure to the surface of the substrate along a direction perpendicular to the substrate. In some embodiments, the conductive structure includes a first conductive structure and a second conductive structure, the first conductive structure being flush with the top surface of the first dielectric layer, and the second conductive structure being located between the first conductive structure and the contact structure, the conductive structure gradually increasing in size from top to bottom along a direction perpendicular to the substrate. In some embodiments, the contact area between the conductive structure and the contact structure is greater than the cross-sectional area of the conductive structure at any location, and also greater than the cross-sectional area of the contact structure at any location. In some embodiments, a top conductive structure is also included, which is located above the conductive structure and covers a portion of the top surface of the first dielectric layer. In some embodiments, the size of the first dielectric layer decreases from top to bottom and then increases, and the first dielectric layer also has an air gap, which is lower than the interface between the conductive structure and the contact structure. In some embodiments, the contact structure includes a first contact structure and a second contact structure, the first contact structure being embedded in the substrate, the second contact structure being located above the first contact structure, and the second contact structure having a gradually decreasing size from top to bottom along a direction perpendicular to the substrate. Another aspect of this disclosure provides a method for forming a semiconductor structure, including: Provide a base; A bit line structure is formed on the substrate. The bit line structure extends along a first direction and is spaced along a second direction. The first direction is perpendicular to the second direction. There is a first opening between adjacent bit line structures. A first conductive layer is formed in the first opening; The first conductive layer is etched along a third direction to form a second opening, and the remaining first conductive layer serves as the second conductive layer. The second conductive layer and the second opening are spaced apart along a first direction, and the third direction is perpendicular to the substrate. The first dielectric layer is filled into the second opening; The second conductive layer is etched back to form the third opening, and the remaining second conductive layer serves as the contact structure. A conductive structure is formed in the third opening, and the conductive structure is located above the contact structure; The dimensions of the contact structure gradually decrease from the top of the contact structure to the surface of the substrate along a direction perpendicular to the substrate. In some embodiments, the conductive structure includes a first conductive structure and a second con