WO-2026091585-A1 - TOTAL VARIATION ANALOG-TO-DIGITAL CONVERTER FOR COLLECTING ELECTROENCEPHALOGRAM

Abstract

Provided in the present invention is a total variation analog-to-digital converter for collecting an electroencephalogram. Firstly, a total variation operator is used to calculate second-order delta encoding, such that the sparsity of an electroencephalogram signal can be more effectively utilized, thereby significantly improving the compression ratio of the electroencephalogram signal. Secondly, a non-switching double-buffer module is designed, such that a second-order delta encoding value can be generated in a simple and efficient manner. Finally, a serialized bitstream generator is designed, such that serialized packaging can be performed on second-order delta data collected by a plurality of parallel channels, which not only exhibits high scalability and is applicable to multi-channel collection, but also enables reliable interfacing with a subsequent synchronous clock wireless transmission system, thus avoiding overheads and latency of synchronous-asynchronous interface coordination, and further improving the signal collection efficiency.

Inventors

• SUN, BIAO
• YANG, JING
• REN, XIAOCHEN
• YAO, CHI

Assignees

• 天津大学

Dates

Publication Date

20260507

Application Date

20250626

Priority Date

20250414

Claims (10)

1. A Total Variation Analog-to-Digital Converter (TV-ADC) for electroencephalogram (EEG) acquisition is characterized in that: the TV-ADC consists of a multiplexer, a fixed double-buffered module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator, and is used to acquire EEG signals; The multiplexer, fixed double-buffered module, incremental counter, and serialized bit stream generator are all controlled by the TV-ADC's global clock CLK ADC ; The multiplexer switches the acquisition channel in each clock cycle and stabilizes the current EEG acquisition signal to support multi-channel parallel acquisition; The fixed double buffer module is responsible for storing and outputting the previous acquisition value of each channel to support the calculation of second-order incremental coding; The DAC controller is used to read the previous acquisition value of the fixed double-buffered module and, in combination with the output of the incremental counter, generate DAC control code; The DAC reads the DAC control code output by the DAC controller, converts it into the EEG signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the fixed double buffer module. The comparator is used to compare the EEG signal to be acquired output from the multiplexer with the EEG signal to be compared output from the DAC, and input the comparison result into the increment counter for increment counting; In each clock cycle, the increment counter reads the output of the comparator, calculates the second-order increment between the current acquired EEG signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator. The serialized bitstream generator stores and converts the signal increment output by the increment counter into a bitstream in each clock cycle, generating the final bitstream output by the TV-ADC.
2. A fully variable analog-to-digital converter according to claim 1, wherein the multiplexer adopts a standard time-division multiplexing structure, the time-division multiplexing structure is implemented by a multiplexer circuit, the switch position is switched once in each clock cycle to select different acquisition channels.
3. A fully variational analog-to-digital converter according to claim 1, wherein the DAC controller comprises an inverting module and a doubling module; the inverting module is implemented using an inverter circuit to invert the sign bit of the input data and output it; the doubling module is implemented using a shift register circuit to shift the input data left by 1 bit, thereby achieving the doubling effect.
4. A fully variable analog-to-digital converter according to claim 3, wherein the DAC controller operates as follows: Assume the data stored in the current fixed double buffer module are as follows: Step 1: Extract the previous two acquisition values of the first channel from FIFO1 and FIFO2 in the fixed double buffer module. and The former is obtained by inverting the input in the inverting module. The latter is input into the doubling module for doubling. Add the two together to get the initial comparison value. Step 2: The increment counter inputs the increment value kΔ, adds it to the initial comparison value, and obtains the value to be compared. Where Δ is the smallest quantization unit of the TV-ADC; and the initial value of the increment is 0Δ. Step 3: Compare the values to be compared As the DAC control code, it is input into the DAC and converted into the corresponding signal to be compared; Step 4: Input the signal to be compared into the comparator and compare it with the signal to be acquired; if the signal to be acquired is greater than the signal to be compared, the increment counter is incremented by 1Δ, and the increment value becomes (k+1)Δ; otherwise, it is decremented by 1Δ, and the increment value becomes (k-1)Δ. Step 5: Repeat steps 2 through 4 until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, stop the loop and use the DAC output as the acquired value. Step 6: Input into FIFO1, and The data stored in the fixed double-buffered module at this time, after inputting into FIFO2, are as follows:
5. A fully variable analog-to-digital converter according to claim 1, wherein the DAC is implemented using an 8-bit capacitor voltage divider structure; and the comparator is a dynamic comparator.
6. A fully variational analog-to-digital converter according to claim 1, wherein the increment counter comprises two modules: a sign register and an 8-bit binary counter; wherein the sign register is composed of a 1-bit register circuit for storing the sign of the increment value, and the 8-bit binary counter is composed of 8 D flip-flops for storing the magnitude of the increment value.
7. According to a total variational analog-to-digital converter (ADC) device as described in claim 6, the increment counter operates as follows: the initial value of the increment is 0Δ; when the comparator output is positive, it is determined that the EEG signal to be acquired is greater than the EEG signal to be compared, then the increment counter is incremented by 1Δ, the sign register is positive, and the increment value becomes (0+1)Δ; when the comparator output is negative, it is determined that the EEG signal to be acquired is less than the EEG signal to be compared, then the increment counter is decremented by 1Δ, the sign register is negative, and the increment value becomes (0-1)Δ; after each judgment, the increment value is output to the DAC controller to generate DAC control code; the above judgment steps are repeated until the difference between the EEG signal to be acquired and the EEG signal to be compared is less than 1Δ, at which point the loop stops, and the sign in the sign register and the value in the 8-bit binary counter are concatenated to obtain the final second-order increment value.
8. A fully variational analog-to-digital converter according to claim 1, wherein the serialized bitstream generator comprises an event judge, an event register, a finite state machine, a bitstream clock generator, and a bitstream packer.
9. According to claim 8, in a fully variable analog-to-digital converter, at the rising edge of each global clock CLK ADC , the event judge reads the increment value from the increment counter and determines whether the increment value forms a second-order increment event; when the increment value is not 0Δ, it is determined to be a second-order increment event, and the increment value is stored in the event register. After all L channels have completed one acquisition, a complete data acquisition frame is formed. After each acquisition frame is completed, the finite state machine generates an enable signal ENA and inputs it to the bit stream clock generator. The clock generator has a built-in ring oscillator, which is dedicated to providing the clock CLK BIT for bit stream packaging. The finite state machine scans the data in the event register and packages the bit stream based on the CLK bit clock to finally generate the TV-ADC data bit stream.
10. According to claim 9, in the serialized bitstream generator, each second-order incremental event requires 9 + log 2 L bits of storage space, where log 2 L bits are used for the numbering of L channels, 1 bit is used for the incremental value sign, and 8 bits are used to store the magnitude of the incremental value.

Description

A total variation analog-to-digital converter for electroencephalogram (EEG) acquisition Cross-reference of related applications This application claims priority to Chinese Patent Application No. 2025104617776, filed on April 14, 2025, entitled “A Total Variation Analog-to-Digital Converter for Electroencephalogram Acquisition,” the entire contents of which are incorporated herein by reference. Technical Field This invention belongs to the field of brain-computer interfaces, and in particular relates to a total variation analog-to-digital converter for electroencephalogram (EEG) acquisition. Background Technology Brain-computer interfaces (BCIs), as a cutting-edge technology connecting the brain to external electronic devices, are revolutionizing neurotherapy, neuroscience research, and human-computer interaction. By monitoring and analyzing brain activity in real time, BCIs offer hope for the recovery of partial function for patients with severe disabilities (such as paralysis and locked-in syndrome). With the help of BCI technology, patients can control external devices through their thoughts, improving their quality of life. Furthermore, BCIs play a crucial role in neuroscience research, helping researchers delve deeper into the neurodynamics of the brain and advancing the understanding and treatment of neurological diseases. The widespread application of BCIs has driven innovation across multiple areas, from basic neuroscience to clinical treatment. Among various sensing technologies in brain-computer interfaces, electroencephalography (EEG) has become the most commonly used signal acquisition method due to its advantages of being non-invasive, convenient, and having high temporal and spatial resolution. EEG can reflect the electrical activity of neuronal populations in the cerebral cortex in real time and is widely used in clinical and research fields. However, with the continuous increase in the number of EEG channels, the acquisition and transmission of EEG signals face unprecedented challenges. With each additional acquisition channel, the amount of data to be transmitted increases dramatically, thus placing higher demands on the system's transmission bandwidth, energy consumption, and processing capabilities. Modern brain-computer interface (BCI) systems generally employ wireless data transmission to ensure users' freedom of movement and minimize disruption to their daily lives. However, with the dramatic increase in data volume, wireless transmission bandwidth has become a bottleneck. Reducing the amount of data transmitted while maintaining data integrity has become crucial to solving this problem. Traditional EEG acquisition systems typically use an architecture combining analog front-end sensors (including a preamplifier stage) and a Nyquist analog-to-digital converter (ADC) to convert analog signals into digital signals for subsequent processing and analysis. However, this traditional architecture suffers from severe energy efficiency issues, especially in scenarios where BCIs require prolonged use and frequent data transmission, where energy efficiency is paramount. Due to limitations in wireless data transmission and battery capacity, traditional Nyquist ADC architectures have not been effectively optimized for energy consumption, resulting in high power consumption and transmission latency. Traditional analog-to-digital conversion methods, based on the Nyquist sampling theorem, require sufficiently high sampling rates to accurately capture the frequency information of EEG signals. Because the spectrum of EEG signals is relatively limited, especially in the high-frequency range, traditional Nyquist sampling methods often generate a large amount of redundant data, increasing the transmission burden and wasting significant power resources. Furthermore, the sparsity characteristics of EEG signals are not fully utilized. Electroencephalogram (EEG) signals exhibit significant sparsity over time, meaning that signal changes are minimal for most of the time, with large fluctuations occurring only at a few moments. To address this redundancy issue, researchers have proposed analog-to-digital converter (ADC) designs based on signal incremental coding (e.g., Delta-ADCs). These designs aim to reduce data transmission overhead and improve system energy efficiency through compressed sampling. Delta-ADCs effectively avoid unnecessary data acquisition during signal silence periods by sampling incremental information only when the input signal crosses a preset threshold, thus saving energy while still efficiently recovering the signal. However, despite the theoretically significant improvement in acquisition efficiency offered by Delta-ADCs, current implementations still face several key challenges. First, the incremental coding method used in Delta-ADCs is not always superior to traditional Nyquist-based analog-to-digital converters (ADCs). In certain applications, especially those with frequent or complex