WO-2026091587-A1 - INTEGER-ORDER DIFFERENCE ANALOG-TO-DIGITAL CONVERTER FOR COLLECTING INTRACRANIAL NEURAL FIELD POTENTIAL

Abstract

Provided in the present invention is an integer-order difference analog-to-digital converter for collecting an intracranial neural field potential. Firstly, an integer-order difference operator is designed to calculate arbitrary integer-order delta encoding, such that the sparsity of an intracranial neural field potential can be more effectively utilized, thereby significantly improving the compression ratio of the intracranial neural field potential; moreover, the integer-order difference analog-to-digital converter has higher flexibility by means of tunable differential orders, and can adapt to a wider range of intracranial neural field potential collection scenarios. Secondly, a multi-stage buffer matrix module is designed, such that an arbitrary integer-order delta encoding value can be generated in a simple and efficient manner. Finally, a serialized bitstream generator is designed, such that serialized packaging can be performed on integer-order delta data collected by a plurality of parallel channels, which not only exhibits high scalability, but also enables reliable interfacing with a subsequent synchronous clock wireless transmission system, thus avoiding overheads and latency of synchronous-asynchronous interface coordination, and further improving the signal collection efficiency.

Inventors

• SUN, BIAO
• XU, Minpeng

Assignees

• 天津大学

Dates

Publication Date

20260507

Application Date

20250626

Priority Date

20250414

Claims (10)

1. An integer order difference analog-to-digital converter (IOD-ADC) for acquiring intracranial neural field potentials comprises a multiplexer, a multi-level buffer matrix module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator, used to acquire intracranial neural field potential signals. The multiplexer, multi-level buffer matrix module, incremental counter, and serialized bit stream generator are all controlled by the global clock CLK ADC of the IOD-ADC; The multiplexer switches the acquisition channel in each clock cycle and stabilizes the current acquisition signal to support multi-channel parallel acquisition; The multi-level buffer matrix module is responsible for storing and outputting the previous acquisition value of each channel to support the calculation of incremental encoding of arbitrary integer order; The DAC controller is used to read the previous acquisition value from the multi-level buffer matrix module and, in conjunction with the output of the incremental counter, generate DAC control code. The DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel into the multi-level buffer matrix module. The comparator is used to compare the signal to be acquired output from the multiplexer with the signal to be compared output from the DAC, and inputs the comparison result into the increment counter for increment counting; In each clock cycle, the increment counter reads the output of the comparator, calculates the integer increment between the current acquired signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator. The serialized bitstream generator stores and converts the signal increment output by the increment counter into a bitstream in each clock cycle, generating the final bitstream output by the IOD-ADC.
2. An integer-order differential analog-to-digital converter according to claim 1, wherein the multiplexer adopts a standard time-division multiplexing structure, the time-division multiplexing structure is implemented by a multiplexer circuit, the switch position is switched once in each clock cycle to select different acquisition channels.
3. An integer-order differential analog-to-digital converter according to claim 1, wherein the multi-level buffer matrix module comprises a storage matrix and a computation matrix; The storage matrix contains r rows and L columns, and data is read in a fixed format. The computation matrix consists of shift units, addition units, and inversion units. The shift units shift the input data bit by bit to the left or right to perform multiplication or division operations. The addition units are used to perform addition operations on the input data. The inversion units are used to invert the sign bit of the input data to obtain the inverted value of the input data. By combining the above computation units, the calculation of the r-order minuend can be realized, and the difference increment value is output to the DAC controller, thus completing the task of the multi-level buffer matrix module.
4. According to claim 3, in each clock cycle, the storage matrix receives data from the DAC input to the left side of the r-th row, and the rightmost data of each row is shifted out of the storage matrix and input into the calculation matrix for calculation. At the same time, the data in the storage matrix moves in a circular motion, that is, the data shifted out of the lower row is simultaneously shifted into the left side of the upper row. Except for the r-th row, which can receive data from the DAC input, the data in other rows can only be shifted in from the corresponding lower row and cannot receive input data from outside the module.
5. An integer-order differential analog-to-digital converter according to claim 1, wherein the DAC controller is used to read the r-th order minuend output by the multi-level buffer matrix module and, in combination with the output of the increment counter, generate DAC control code.
6. An integer-order differential analog-to-digital converter according to claim 1, wherein the DAC controller operates as follows: The first step is to calculate the r-th order minuend y_i using a multi-level buffer matrix module; Step 2: The increment counter inputs the increment value kΔ and adds it to the r-order minuend y i to obtain the value to be compared y i + kΔ, where Δ is the smallest quantization unit of the IOD-ADC and the initial value of the increment value is 0Δ. Step 3: Use the value to be compared, y _{i +kΔ}, as the DAC control code, input it into the DAC, and convert it into the corresponding signal to be compared. Step 4: Input the signal to be compared into the comparator and compare it with the signal to be acquired; if the signal to be acquired is greater than the signal to be compared, the increment counter is incremented by 1Δ, and the increment value becomes (k+1)Δ; otherwise, it is decremented by 1Δ, and the increment value becomes (k-1)Δ. Step 5: Repeat steps 2 through 4 until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, stop the loop and use the DAC output as the acquired value. Step 6: Store back into the multilevel buffer matrix module and update the value of each row in the multilevel buffer matrix module.
7. An integer-order differential analog-to-digital converter according to claim 1, wherein the DAC is implemented using an 8-bit capacitor voltage divider structure; and the comparator is a dynamic comparator.
8. An integer-order differential analog-to-digital converter according to claim 1, wherein the increment counter includes a sign register and an 8-bit binary counter, the sign register being composed of a 1-bit register circuit for storing the sign of the increment value, and the 8-bit binary counter being composed of 8 D flip-flops for storing the magnitude of the increment value.
9. According to claim 8, the integer-order differential analog-to-digital converter (ADC) device has the following operation: the initial value of the increment value is 0Δ; when the comparator output is positive, it is determined that the signal to be acquired is greater than the signal to be compared, so the increment counter is incremented by 1Δ, the sign register is positive, and the increment value becomes (0+1)Δ; when the comparator output is negative, it is determined that the signal to be acquired is less than the signal to be compared, so the increment counter is decremented by 1Δ, the sign register is negative, and the increment value becomes (0-1)Δ; after each judgment, the increment value is output to the DAC controller to generate DAC control code; the above judgment steps are repeated until the difference between the signal to be acquired and the signal to be compared is less than 1Δ, at which point the loop stops, and the sign in the sign register and the value in the 8-bit binary counter are concatenated to obtain the final integer-order increment value.
10. An integer-order differential analog-to-digital converter according to claim 1, wherein the serialized bitstream generator comprises an event judge, an event register, a finite state machine, a bitstream clock generator, and a bitstream packer.

Description

An integer-order differential analog-to-digital converter for intracranial neural field potential acquisition Cross-reference of related applications This application claims priority to Chinese Patent Application No. 2025104647273, filed on April 14, 2025, entitled "An Integer-Order Differential Analog-to-Digital Converter for Intracranial Neural Field Potential Acquisition", the entire contents of which are incorporated herein by reference. Technical Field This invention belongs to the field of brain-computer interfaces, and in particular relates to an integer-order differential analog-to-digital converter for acquiring intracranial neural field potentials. Background Technology As a disruptive technology at the intersection of neuroscience and engineering, invasive brain-computer interfaces (BCIs) are reshaping the paradigm of rehabilitation for paralyzed patients and treatment for neurological diseases by directly capturing electrical activity in the cerebral cortex through implanted electrode arrays. This technology can not only interpret motor intention signals, helping spinal cord injury patients control robotic arms to perform grasping actions, but also intervene in abnormal brain electrical rhythms through closed-loop electrical stimulation, providing precise treatment options for tremor control in Parkinson's disease. Its high spatiotemporal resolution signal decoding capabilities enable researchers to explore the neural circuit mechanisms of cognitive function with single-neuron precision, accelerating the deep integration of brain-computer interface theory and clinical translational research. In invasive systems, intracranial neural field potentials, as core bioelectrical signals reflecting the synchronous firing of neuronal clusters, directly determine the performance boundaries of brain-computer interfaces through their acquisition quality. These signals are formed by the superposition of postsynaptic potentials from cortical pyramidal cells, exhibiting microvolt-level amplitudes and kilohertz-level dynamic ranges. To accurately capture their millisecond-level transient fluctuations, implanted electrodes must penetrate the pia mater to contact the cortical surface, and low-noise amplifiers and high-precision filtering circuits must be used to eliminate electromyographic artifacts. However, this invasive acquisition method presents multiple engineering challenges regarding biocompatibility, long-term electrode stability, and signal fidelity; even the introduction of minute noise can distort the spatiotemporal characteristics of neural coding. Traditional acquisition architectures typically employ Nyquist analog-to-digital converters (ADCs) for uniform sampling of intracranial neural field potentials across the entire frequency band. This design suffers from severe energy efficiency bottlenecks when dealing with large-scale parallel acquisition across multiple channels. Since the energy of neural electrical signals is primarily concentrated below 300Hz, and there is strong correlation between adjacent sampling points, the forced high-frequency sampling strategy results in over 70% of the data being redundant. This not only leads to inefficient use of wireless transmission bandwidth but also causes a dramatic increase in the power density of implanted devices. When the number of channels exceeds 128, the system's static power consumption may exceed the 10mW threshold, causing local tissue temperature rise and accelerating the aging of electrode encapsulation materials, seriously threatening the long-term implantation safety of the device. To overcome energy efficiency barriers, event-driven incremental coding analog-to-digital conversion technologies (such as Delta-ADC) have emerged. This solution innovatively introduces a dynamic threshold comparison mechanism, triggering quantization only when the signal amplitude exceeds a preset threshold. This adaptive sampling strategy fully utilizes the sparsity of neural signals in the time dimension, intelligently distinguishing the spike waves during epileptic seizures from background noise. This results in data throughput reductions of over 82% in scenarios such as Parkinson's disease monitoring and rhythm acquisition. By constructing a multi-level differential coding tree, the system can simultaneously extract signal amplitude abrupt changes and slope variations, significantly reducing single-channel power consumption and extending the battery life of implanted devices while maintaining action potential waveform details. However, despite the theoretically significant improvement in acquisition efficiency offered by Delta-ADCs, current implementations still face several key challenges. First, the incremental coding method used in Delta-ADCs is not always superior to traditional Nyquist-based analog-to-digital converters (ADCs). In certain applications, especially those with frequent or complex signal changes, Delta-ADCs may actually outperform tradition