WO-2026091839-A1 - CHARGE PUMP CIRCUIT AND CHARGE PUMP SYSTEM

WO2026091839A1WO 2026091839 A1WO2026091839 A1WO 2026091839A1WO-2026091839-A1

Abstract

A charge pump circuit and a charge pump system. The charge pump circuit comprises: a comparison unit, which is adapted to receive a reference signal and a voltage-divided signal and compare the reference signal with the voltage-divided signal, so as to obtain a feedback signal; a signal processing unit, which is connected to the comparison unit and is adapted to receive the feedback signal and process the feedback signal, so as to obtain a processed feedback signal; a driving unit, which is connected to the signal processing unit and is adapted to receive a clock signal and the processed feedback signal and perform a NOR operation on the clock signal and the processed feedback signal, so as to obtain a driving signal; and a charge pump unit, which is connected to the driving unit and is adapted to receive the driving signal and turn on or off under the control of the driving signal. By adjusting the feedback signal by means of the signal processing unit, a processed feedback signal with an increased duty cycle can be obtained, thereby improving the boost performance of the charge pump.

Inventors

JIA, Min

Assignees

上海华虹宏力半导体制造有限公司

Dates

Publication Date: 20260507
Application Date: 20250902
Priority Date: 20241104

Claims (14)

A charge pump circuit, characterized in that it comprises: The comparison unit is adapted to receive a reference signal and a voltage divider signal, and compare the reference signal and the voltage divider signal to obtain a feedback signal; A signal processing unit, connected to the comparison unit, is adapted to receive the feedback signal and process the feedback signal to obtain a processed feedback signal, wherein the duty cycle of the processed feedback signal is greater than the duty cycle of the original feedback signal. A driving unit, connected to the signal processing unit, is adapted to receive a clock signal and a processed feedback signal, and to perform a NOR operation on the clock signal and the processed feedback signal to obtain a driving signal. And a charge pump unit, connected to the drive unit, adapted to receive the drive signal and to be turned on or off under the control of the drive signal; During the period when the clock signal is in the second level state, the processed feedback signal remains in the first level state; the first level state and the second level state are logically opposite.
The charge pump circuit as described in claim 1 is characterized in that the signal processing unit is further adapted to receive a processing signal and perform delay processing on the feedback signal based on the processing signal to obtain the processed feedback signal.
The charge pump circuit as described in claim 2 is characterized in that the processed feedback signal is synchronized with the clock signal.
The charge pump circuit as described in claim 3, wherein the signal processing unit comprises: A pulse signal generation module, connected to the comparison unit, is adapted to receive and process signals and generate pulse signals according to the processed signals; The sampling module, connected to the pulse signal generation module, is adapted to receive the feedback signal and the pulse signal, and to sample the feedback signal according to the pulse signal to obtain the processed feedback signal synchronized with the clock signal.
The charge pump circuit as described in claim 4, wherein the pulse signal generation module comprises: The first submodule is adapted to receive the processing signal and process the rising edge of the processing signal to obtain a first subpulse signal; The second submodule, connected in parallel with the first submodule, is adapted to receive the processing signal and process the falling edge of the processing signal to obtain a second sub-pulse signal; the merging submodule, connected with the first submodule and the second submodule, is adapted to receive the first sub-pulse signal and the second sub-pulse signal and merge the first sub-pulse signal and the second sub-pulse signal to obtain the pulse signal.
The charge pump circuit as described in claim 5, wherein the first sub-module comprises: a first inverter, a first delay unit, and a first NOR gate; wherein: The input terminal of the first inverter is adapted to receive the processed signal, and the output terminal of the first inverter is connected to the input terminal of the first delay unit; the output terminal of the first delay unit is connected to the second input terminal of the first NOR gate. The first input terminal of the first NOR gate is adapted to receive the processed signal, and the output terminal of the first NOR gate is adapted to output the first sub-pulse signal.
The charge pump circuit as described in claim 5, wherein the second submodule comprises: a second inverter, a second delay unit, and a second NOR gate; wherein: The input terminal of the second inverter is adapted to receive the processed signal, and the output terminal of the second inverter is connected to the input terminal of the second delay unit; the output terminal of the second delay unit is connected to the second input terminal of the second NOR gate. The first input terminal of the second NOR gate is adapted to receive the processed signal, and the output terminal of the second NOR gate is adapted to output the second sub-pulse signal.
The charge pump circuit as described in claim 5, wherein the merging submodule includes: a third NOR gate; The first input terminal of the third NOR gate is adapted to receive the first sub-pulse signal, the second input terminal of the third NOR gate is adapted to receive the second sub-pulse signal, and the output terminal of the third NOR gate is adapted to output the pulse signal.
The charge pump circuit as described in claim 4, wherein the sampling module comprises: a trigger; The first input terminal of the trigger is adapted to receive the feedback signal, the second input terminal of the trigger is adapted to receive the pulse signal, and the output terminal of the trigger is adapted to output the feedback signal after synchronization processing.
The charge pump circuit as described in claim 1, characterized in that the driving unit comprises: a fourth NOR gate and a third inverter; wherein: The first input terminal of the fourth NOR gate is adapted to receive the clock signal, the second input terminal of the fourth NOR gate is adapted to receive the processed feedback signal, and the output terminal of the fourth NOR gate is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the charge pump unit.
The charge pump circuit as described in claim 1, wherein the comparison unit comprises: a comparator; a first input terminal of the comparator is adapted to receive a reference signal, a second input terminal of the comparator is adapted to receive a voltage divider signal, and an output terminal of the comparator is adapted to output a feedback signal.
The charge pump circuit as described in claim 1 is characterized in that it further includes: a voltage divider circuit connected to the second input terminal of the comparator, adapted to generate a voltage divider signal.
The charge pump circuit as described in claim 1 is characterized in that it further includes: a reference circuit connected to the first input terminal of the comparator, adapted to generate a reference signal.
A charge pump system, characterized in that it comprises a plurality of cascaded charge pump circuits as described in any one of claims 1 to 13, each charge pump circuit comprising an input terminal and an output terminal, wherein the output terminal of the preceding charge pump circuit is connected to the input terminal of the following charge pump circuit.

Description

Charge pump circuit and charge pump system This application claims priority to Chinese Patent Application No. 202411567733.3, filed on November 4, 2024, entitled “Charge Pump Circuit and Charge Pump System”, the entire contents of which are incorporated herein by reference. Technical Field This invention relates to the field of semiconductor manufacturing, and more particularly to a charge pump circuit and a charge pump system. Background Technology A charge pump circuit is a device used for voltage conversion, which can realize voltage transformation, such as boost, buck, and inversion. Charge pump circuits boost voltage by charging and discharging capacitors through switches. Since charge pump circuits do not have inductors for energy storage and have weak driving capabilities, they can be used in low-current applications and are therefore often used in flash memory for voltage conversion. However, current charge pump circuits have poor boost performance. Summary of the Invention The technical problem solved by this invention is how to improve the boost performance of a charge pump circuit. To address the aforementioned technical problems, embodiments of the present invention provide a charge pump circuit, comprising: The comparison unit is adapted to receive a reference signal and a voltage divider signal, and compare the reference signal and the voltage divider signal to obtain a feedback signal; A signal processing unit, connected to the comparison unit, is adapted to receive the feedback signal and process the feedback signal to obtain a processed feedback signal, wherein the duty cycle of the processed feedback signal is greater than the duty cycle of the original feedback signal. A driving unit, connected to the signal processing unit, is adapted to receive a clock signal and a processed feedback signal, and to perform a NOR operation on the clock signal and the processed feedback signal to obtain a driving signal. And a charge pump unit, connected to the drive unit, adapted to receive the drive signal and to be turned on or off under the control of the drive signal; During the period when the clock signal is in the second level state, the processed feedback signal remains in the first level state; the first level state and the second level state are logically opposite. Optionally, the signal processing unit is further adapted to receive a processing signal and perform delay processing on the feedback signal based on the processing signal to obtain the processed feedback signal. Optionally, the processed feedback signal is synchronized with the clock signal. Optionally, the signal processing unit includes: a pulse signal generation module connected to the comparison unit, adapted to receive the processing signal and generate a pulse signal according to the processing signal; and a sampling module connected to the pulse signal generation module, adapted to receive the feedback signal and the pulse signal, and sample the feedback signal according to the pulse signal to obtain the processed feedback signal synchronized with the clock signal. Optionally, the pulse signal generation module includes: a first submodule, adapted to receive the processing signal and process the rising edge of the processing signal to obtain a first subpulse signal; a second submodule, connected in parallel with the first submodule, adapted to receive the processing signal and process the falling edge of the processing signal to obtain a second subpulse signal; and a merging submodule, connected to the first submodule and the second submodule, adapted to receive the first subpulse signal and the second subpulse signal and merge the first subpulse signal and the second subpulse signal to obtain the pulse signal. Optionally, the first submodule includes: a first inverter, a first delay unit, and a first NOR gate; wherein: the input terminal of the first inverter is adapted to receive the processed signal, and the output terminal of the first inverter is connected to the input terminal of the first delay unit; the output terminal of the first delay unit is connected to the second input terminal of the first NOR gate; the first input terminal of the first NOR gate is adapted to receive the processed signal, and the output terminal of the first NOR gate is adapted to output a first sub-pulse signal. Optionally, the second submodule includes: a second inverter, a second delay unit, and a second NOR gate; wherein: the input terminal of the second inverter is adapted to receive the processed signal, and the output terminal of the second inverter is connected to the input terminal of the second delay unit; the output terminal of the second delay unit is connected to the second input terminal of the second NOR gate; the first input terminal of the second NOR gate is adapted to receive the processed signal, and the output terminal of the second NOR gate is adapted to output a second sub-pulse signal. Optionally, the merging submodule in