WO-2026091859-A1 - SHIFT REGISTER AND DRIVING METHOD THEREFOR, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE

WO2026091859A1WO 2026091859 A1WO2026091859 A1WO 2026091859A1WO-2026091859-A1

Abstract

The present application relates to the technical field of display, and provides a shift register and a driving method therefor, a gate driving circuit, and a display device. The shift register comprises: an input circuit, a first control circuit, and an output circuit; the input circuit is separately connected to an input signal line and a first node, and is configured to write an input signal into the first node under the control of an input signal of the input signal line; the first control circuit is separately electrically connected to the first node and a first power signal line, and is configured to disconnect the first power signal line from the first node in a touch stage; and the output circuit is separately electrically connected to the first node, a clock signal line, and an output signal line, and is configured to write a clock signal of the clock signal line into the output signal line under the control of a voltage of the first node. The horizontal stripe defects of display panels can be ameliorated, and the image quality of the display panels can be improved.

Inventors

WU, Zhongshan
GUO, Jian Dong
WANG, XIAOYUAN
YIN, XIAOFENG
WAN, BIN

Assignees

京东方科技集团股份有限公司
重庆京东方光电科技有限公司

Dates

Publication Date: 20260507
Application Date: 20250903
Priority Date: 20241030

Claims (20)

A shift register, wherein the shift register includes: an input circuit, a first control circuit, and an output circuit; The input circuit is connected to the input signal line and the first node respectively, and is configured to write the input signal into the first node under the control of the input signal on the input signal line; The first control circuit is electrically connected to the first node and the first power signal line respectively, and is configured to disconnect the connection between the first power signal line and the first node during the touch phase. The output circuit is electrically connected to the first node, the clock signal line, and the output signal line, respectively, and is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node.
According to claim 1, the shift register, wherein the first control circuit includes a reset module and a pull-down module; The reset module is electrically connected to the reset signal line, the first node, and the first power signal line, and is configured to control the connection and disconnection between the first power signal line and the first node under the control of the reset signal of the reset signal line. The pull-down module is electrically connected to the second node, the first node, and the first power signal line, respectively, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the voltage of the second node.
According to claim 2, the shift register, wherein the reset module includes a first transistor; The control electrode of the first transistor is electrically connected to the first sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the first sub-signal line. The first sub-signal line is the signal line connected to the output control terminal of the target register; the target register is a register cascaded with the shift register, and the target register is located at the next level of the shift register.
According to claim 2, the shift register, wherein the reset module includes a second transistor; The control electrode of the second transistor is electrically connected to the second sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the second sub-signal line.
According to claim 2, the shift register, wherein the second node includes a first pull-down node and a second pull-down node, and the pull-down module includes a first pull-down unit and a second pull-down unit; The first pull-down unit is electrically connected to the first pull-down node, the first node, and the first power signal line, respectively, and is configured to control the on/off state of the first power signal line and the first node under the control of the voltage of the first pull-down node; The second pull-down unit is electrically connected to the second pull-down node, the first node, and the first power signal line, respectively, and is configured to control the on/off state of the first power signal line and the first node under the control of the voltage of the second pull-down node.
The shift register according to claim 5, wherein the first pull-down unit includes a third transistor; The control electrode of the third transistor is electrically connected to the first pull-down node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line.
The shift register according to claim 5, wherein the second pull-down unit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the second pull-down node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line.
The shift register according to any one of claims 1-7, wherein the shift register further includes a first noise reduction circuit; The first noise reduction circuit is electrically connected to the first power signal line, the second node, and the second power signal line, respectively, and is configured to write the second power signal of the second power signal line into the second node under the control of the first power signal during the touch phase.
According to claim 8, the shift register includes a first pull-down node and a second pull-down node, and the first noise reduction circuit includes a first noise reduction module and a second noise reduction module. The first noise reduction module is electrically connected to the first power signal line, the first pull-down node, and the second power signal line, respectively, and is configured to write the second power signal into the first pull-down node under the control of the first power signal during the touch phase. The second noise reduction module is electrically connected to the first power signal line, the second pull-down node, and the second power signal line respectively, and is configured to write the second power signal into the second pull-down node under the control of the first power signal during the touch phase.
According to claim 9, the shift register, wherein the first noise reduction module includes a fifth transistor; The control electrode of the fifth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the first pull-down node, and the second electrode is electrically connected to the second power signal line.
According to claim 9, the shift register, wherein the second noise reduction module includes a sixth transistor; The control electrode of the sixth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the second pull-down node, and the second electrode is electrically connected to the second power signal line.
The shift register according to any one of claims 1-7, wherein the shift register further includes a second noise reduction circuit; The second noise reduction circuit is electrically connected to the first power signal line, the second power signal line, and the output signal line, respectively, and is configured to, during the touch phase, write the second power signal of the second power signal line into the output signal line under the control of the first power signal.
The shift register according to claim 12, wherein the second noise reduction circuit includes a seventh transistor; The control electrode of the seventh transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the output signal line, and the second electrode is electrically connected to the second power signal line.
The shift register according to any one of claims 1-7, wherein the shift register further includes an output control circuit and a third noise reduction circuit; The output control circuit is electrically connected to the first node, the clock signal line, and the output control line, respectively, and is configured to write the clock signal into the output control line under the control of the voltage of the first node. The third noise reduction circuit is electrically connected to the first power signal line, the second power signal line, and the output control line, respectively, and is configured to write the second power signal of the second power signal line into the output control line under the control of the first power signal during the touch phase.
The shift register according to claim 14, wherein the third noise reduction circuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the first power signal line, the first electrode is electrically connected to the output control line, and the second electrode is electrically connected to the second power signal line.
A gate driving circuit, wherein the gate driving circuit includes a plurality of cascaded shift registers as described in any one of claims 1-15.
A display device, wherein the display device includes the gate driving circuit as described in claim 16.
A driving method, wherein the method is used to control a shift register as described in any one of claims 1-15, the driving method comprising: In the first display stage, an input signal with a first level is written to the input signal line so that the input circuit writes the input signal with the first level to the first node; During the touch phase, a first power signal with a first level is written to the first power signal line, and the first control circuit is controlled to disconnect the connection between the first power signal line and the first node.
The driving method according to claim 18, wherein, after the touch phase, the method further comprises: In the second display stage, a first power signal with a second level is written to the first power signal line, and a clock signal is written to the clock signal line so that the output circuit writes the clock signal to the output signal line. The first display stage also includes: Write the first power signal with the second level to the first power signal line; wherein the signals corresponding to the first level and the second level are out of phase.
According to the driving method of claim 19, the shift register further includes a pull-up circuit, which is electrically connected to the third power supply signal line and the second node respectively. The first display stage also includes: Write a third power signal with a first level to the third power signal line so that the pull-up circuit can connect the second node and the third power signal line, and write the third power signal with the first level to the second node. The second display stage also includes: Write the third power signal with a first level to the third power signal line so that the pull-up circuit conducts the connection between the second node and the third power signal line, and write the third power signal with a first level to the second node; The touch phase also includes: Write a third power signal with a second level to the third power signal line to cause the pull-up circuit to disconnect the connection between the second node and the third power signal line; Wherein, the time point at which the first power signal transitions from the second level to the first level is delayed by a first duration relative to the time point at which the third power signal transitions from the first level to the second level; the time point at which the first power signal transitions from the first level to the second level is advanced by a first duration relative to the time point at which the third power signal transitions from the second level to the first level. Wherein, the first duration is greater than or equal to the line scan duration, and less than or equal to twice the line scan duration; the line scan duration represents the time required to scan one line of pixels.

Description

Shift registers and their driving methods, gate driving circuits and display devices Cross-reference of related applications This application claims priority to Chinese Patent Application No. 202411535959.5, filed on October 30, 2024, entitled "Shift Register and Driving Method Thereof, Gate Driving Circuit and Display Device", the entire contents of which are incorporated herein by reference. Technical Field This application relates to the field of display technology, and in particular to a shift register and its driving method, gate driving circuit and display device. Background Technology As users increasingly demand more diverse functions from computer products such as laptops (Notebooks, NBs), and as the application of functions such as finger touch and active pen touch becomes more widespread, the advantages of embedded touch, such as in-cell touch display panels, are becoming increasingly prominent. Embedded touch typically employs an in-frame touch (LHB) mode that alternates between a display phase and a touch phase. During the touch phase, the pull-up node (PU) voltage of the outgoing row needs to be kept high until the end of the touch phase, so that the shift register can output signals normally. However, due to transistor leakage in the PU nodes of the current shift register, the voltage of the PU node in the row that enters the pit is lower than that of the PU node in the row that does not enter the pit when it leaves the pit. This causes the output signal of the shift register to decrease, resulting in insufficient charging of the corresponding pixel row and causing poor horizontal stripe quality on the display panel. Summary of the Invention This application provides a shift register and its driving method, gate driving circuit and display device, which can solve the problem of horizontal lines on the display panel caused by voltage drop at the PU node of the shift register during the touch stage. In a first aspect, this application provides a shift register, which includes: an input circuit, a first control circuit, and an output circuit; The input circuit is connected to the input signal line and the first node respectively, and is configured to write the input signal into the first node under the control of the input signal on the input signal line; The first control circuit is electrically connected to the first node and the first power signal line respectively, and is configured to disconnect the connection between the first power signal line and the first node during the touch phase. The output circuit is electrically connected to the first node, the clock signal line, and the output signal line, respectively, and is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node. Optionally, the first control circuit includes a reset module and a pull-down module; The reset module is electrically connected to the reset signal line, the first node, and the first power signal line, and is configured to control the connection and disconnection between the first power signal line and the first node under the control of the reset signal of the reset signal line. The pull-down module is electrically connected to the second node, the first node, and the first power signal line, respectively, and is configured to control the connection and disconnection of the first power signal line and the first node under the control of the voltage of the second node. Optionally, the reset module includes a first transistor; The control electrode of the first transistor is electrically connected to the first sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the first sub-signal line. Wherein, the first sub-signal line is the signal line connected to the output control terminal of the target register; the target register is a register cascaded with the shift register, and the target register is located at the next level of the shift register. Optionally, the reset module includes a second transistor; The control electrode of the second transistor is electrically connected to the second sub-signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power signal line; the reset signal line includes the second sub-signal line. Optionally, the second node includes a first drop-down node and a second drop-down node, and the drop-down module includes a first drop-down unit and a second drop-down unit; The first pull-down unit is electrically connected to the first pull-down node, the first node, and the first power signal line, respectively, and is configured to control the on/off state of the first power signal line and the first node under the control of the voltage of the first pull-down node; The second pull-d