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WO-2026091862-A1 - ARRAY SUBSTRATE AND DISPLAY DEVICE

WO2026091862A1WO 2026091862 A1WO2026091862 A1WO 2026091862A1WO-2026091862-A1

Abstract

An array substrate and a display device. The array substrate comprises a base substrate (10) and at least one test unit (20). The base substrate (10) has a display area (11) and a non-display area (12). The test unit (20) is located in the non-display area (12), and the test unit (20) comprises a test element (21), test pads (22) and traces (23), wherein each port of the test element (21) corresponds to a test pad (22) and a trace (23), and is connected to the corresponding test pad (22) by means of the corresponding trace (23); and the orthographic projections of the test pads (22) on the base substrate are circular.

Inventors

  • YE, XIN
  • ZHANG, KAI
  • SHI, ZHIJIE
  • ZENG, Jiayuan
  • LI, Songbao
  • ZHOU, Junhong

Assignees

  • 京东方科技集团股份有限公司
  • 成都京东方光电科技有限公司

Dates

Publication Date
20260507
Application Date
20250904
Priority Date
20241030

Claims (17)

  1. An array substrate, comprising: A substrate (10) having a display area (11) and a non-display area (12) located on one side of the display area (11); and At least one test unit (20) is located in the non-display area (12); the test unit (20) includes a test element (21), a test pad (22) and a trace (23); each port of the test element (21) corresponds to the test pad (22) and the trace (23), and is connected to the corresponding test pad (22) through the corresponding trace (23); the orthographic projection of the test pad (22) on the substrate (10) is circular.
  2. According to claim 1, the array substrate, wherein the test element (21) is a transistor with three ports, and the test unit (20) includes three test pads (22) and three traces (23), wherein the three test pads (22) and the three traces (23) correspond one-to-one with the three ports of the test element (21).
  3. According to claim 2, the array substrate wherein the centers of the orthographic projections of the three test pads (22) onto the substrate (10) are not collinear.
  4. According to claim 3, the orthographic projection of two of the test pads (22) on the substrate (10) is located on a first side of the orthographic projection of the test element (21) on the substrate (10); the orthographic projection of the other test pad (22) on the substrate (10) is located on a second side of the orthographic projection of the test element (21) on the substrate (10), the second side being opposite to the first side.
  5. According to claim 4, the array substrate includes a non-display area (12) that corresponds to a test unit (20) and the test unit (20) is located within the corresponding test area (120); the orthographic projection of the test area (120) on the substrate (10) is a triangle.
  6. According to claim 5, the center line connecting the two test pads (22) located on the same side of the test element (21) is parallel to one side of the triangle.
  7. According to claim 5, the array substrate includes a plurality of test units (20), and a plurality of test areas (120) are arranged in at least one row and multiple columns; the orthographic projection of two adjacent test areas (120) in the same row onto the substrate (10) is a point-symmetric pattern.
  8. According to claim 6, the array substrate is wherein the plurality of test areas (120) are arranged in at least two rows; the orthographic projection of two adjacent test areas (120) in the same column onto the substrate (10) is an axisymmetric figure, and the axis of symmetry is parallel to the row direction.
  9. According to any one of claims 3-8, the orthographic projection of the three test pads (22) on the substrate (10) is a circle of equal size, and the distance between the centers of the orthographic projections of the three test pads (22) on the substrate (10) is equal.
  10. According to claim 2, the array substrate wherein the three test pads (22) are arranged at intervals along a first direction on the orthogonal projection of the substrate (10).
  11. According to the array substrate of claim 10, the orthographic projections of the three test pads (22) on the substrate (10) are located on the same side of the orthographic projection of the test element (21) on the substrate (10); the orthographic projections of the test pads (22) and the test element (21) on the substrate (10) are spaced apart along a second direction, the second direction intersecting the first direction.
  12. According to claim 11, the array substrate includes a non-display area (12) that corresponds to a test unit (20) and the test unit (20) is located within the corresponding test area (120); the orthographic projection of the test area (120) on the substrate (10) is rectangular.
  13. According to claim 12, the array substrate includes a plurality of test units (20) and a plurality of test areas (120) arranged in an array.
  14. According to any one of claims 10-13, the orthographic projection of the three test pads (22) onto the substrate (10) is a circle of equal size, and the centers of the orthographic projections of the three test pads (22) onto the substrate (10) are collinear.
  15. According to any one of claims 7, 8, and 13, the array substrate wherein one side of the orthographic projection of two adjacent test areas (120) onto the substrate (10) coincides.
  16. The array substrate according to any one of claims 2-8 and 10-13 further comprises: A pixel circuit is located in the display area (11); the pixel circuit includes multiple thin-film transistors, and the test element (21) is consistent with the thin-film transistors in terms of material, thickness and aspect ratio.
  17. A display device comprising an array substrate as claimed in any one of claims 1-16.

Description

Array substrate and display device Cross-reference of related applications This disclosure claims priority to Chinese patent application No. 2024115354708, filed on October 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field This disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Technology The array substrate is the main structure of a display and requires relevant testing to ensure product yield. Current testing of array substrates includes Electronic Performance Measurement (EPM) of the Thin Film Transistor (TFT). EPM sets up TFT test element groups (TEGs) on the array substrate, and customized probes from the EPM equipment are inserted into the square pads of the TEGs for testing. If even one probe deviates from the square pad, the entire substrate risks being scrapped. Summary of the Invention This disclosure provides an array substrate and a display device, which aims to at least partially solve the problem of probes easily deviating from the pads. In a first aspect of this disclosure, an array substrate is provided, the array substrate comprising: a substrate having a display area and a non-display area located on one side of the display area; and at least one test unit located within the non-display area; the test unit comprising a test element, a test pad, and a trace; each port of the test element corresponding to the test pad and the trace, and connected to the corresponding test pad through the corresponding trace; the orthographic projection of the test pad on the substrate is circular. In some embodiments, the test element is a transistor with three ports, and the test unit includes three test pads and three traces, each of which corresponds to one of the three ports of the test element. In some embodiments, the centers of the orthographic projections of the three test pads onto the substrate are not collinear. In some embodiments, the orthographic projections of two of the test pads on the substrate are located on a first side of the orthographic projection of the test element on the substrate; the orthographic projection of the other test pad on the substrate is located on a second side of the orthographic projection of the test element on the substrate, the second side being opposite to the first side. In some embodiments, the non-display area includes test areas corresponding one-to-one with the test units, and the test units are located within the corresponding test areas; the orthographic projection of the test area on the substrate is a triangle. In some embodiments, the line connecting the centers of the two test pads located on the same side of the test element is parallel to one side of the triangle. In some embodiments, the array substrate includes a plurality of test units, and the plurality of test areas are arranged in at least one row and multiple columns; the orthographic projection of two adjacent test areas in the same row onto the substrate is a point-symmetric pattern. In some embodiments, the plurality of test areas are arranged in at least two rows; the orthographic projection of two adjacent test areas in the same column onto the substrate is an axisymmetric figure, and the axis of symmetry is parallel to the row direction. In some embodiments, the orthographic projections of the three test pads onto the substrate are circles of equal size, and the distance between the centers of the orthographic projections of the three test pads onto the substrate is equal. In some embodiments, the orthographic projections of the three test pads on the substrate are spaced apart along a first direction. In some embodiments, the orthographic projections of the three test pads on the substrate are located on the same side of the orthographic projections of the test element on the substrate; the orthographic projections of the test pads and the test element on the substrate are spaced apart along a second direction, which intersects the first direction. In some embodiments, the non-display area includes test areas corresponding one-to-one with the test units, and the test units are located within the corresponding test areas; the orthographic projection of the test area on the substrate is rectangular. In some embodiments, the array substrate includes a plurality of the test units, and the plurality of test areas are arranged in an array. In some embodiments, the orthographic projections of the three test pads onto the substrate are circles of equal size, and the centers of the orthographic projections of the three test pads onto the substrate are collinear. In some embodiments, one side of the orthographic projection of two adjacent test areas onto the substrate coincides. In some embodiments, the array substrate further includes: a pixel circuit located in the display area; the pixel circuit includes a plurality of thin-film transistors, and the test element has the same