WO-2026091867-A1 - DISPLAY SUBSTRATE AND DISPLAY APPARATUS

WO2026091867A1WO 2026091867 A1WO2026091867 A1WO 2026091867A1WO-2026091867-A1

Abstract

The present disclosure belongs to the technical field of display. Provided are a display substrate and a display apparatus. The display substrate in the present disclosure comprises: a base substrate, which is divided into a display area and a peripheral area located on at least one side of the display area; and a gate driving circuit and a frame start signal line, which are arranged on the base substrate and located in the peripheral area, wherein the frame start signal line is configured to provide a frame start signal for at least one shift register in the gate driving circuit, the frame start signal line comprises at least two signal line segments that are arranged in a disconnected manner, and a transfer electrode that connects two signal line segments arranged adjacent to each other, and the transfer electrode and the signal line segments are located in different layers.

Inventors

TIAN, Zihan
CHENG, LIANG
LIU, XIN
JIANG, PENG
DING, JUN
HUANG, Junling
WANG, HUI
LIU, JIANTAO

Assignees

京东方科技集团股份有限公司
武汉京东方光电科技有限公司

Dates

Publication Date: 20260507
Application Date: 20250904
Priority Date: 20241031

Claims (18)

A display substrate comprising: The substrate is divided into a display area and a peripheral area located on at least one side of the display area; A gate drive circuit and a frame enable signal line are disposed on the substrate, located in the peripheral region. The frame enable signal line is configured to provide a frame enable signal to at least one shift register in the gate drive circuit. The frame enable signal line includes at least two disconnected signal segments and a transition electrode connecting two adjacent signal segments; the transition electrode and the signal segments are located on different layers.
The display substrate according to claim 1, further comprising: A first conductive layer is disposed on the substrate, and the gates of each thin-film transistor of the shift register are located in the first conductive layer; A first interlayer insulating layer is disposed on the side of the first conductive layer away from the substrate. The second conductive layer is disposed on the side of the first interlayer insulating layer away from the first conductive layer, and the source and drain of each thin film transistor of the shift register are located in the second conductive layer. The second interlayer insulating layer is disposed on the side of the second conductive layer that is opposite to the first interlayer insulating layer; The third conductive layer is disposed on the side of the second interlayer insulating layer away from the second conductive layer, and the common electrode of the pixel unit located in the display area is located in the third conductive layer.
According to claim 2, the display substrate, wherein the transition electrode includes a first transition portion, a second transition portion, and a third transition portion; the first transition portion and the second transition portion are located in the third conductive layer, the third transition portion is located in the second conductive layer, and the first transition portion and the second transition portion are respectively connected to the third transition portion through at least one first connection via and at least one second connection via; the first connection via and the second connection via both penetrate the second interlayer insulating layer; The signal line segment is located in the first conductive layer. For two adjacent signal line segments, one is connected to the first adapter through at least one third connecting via, and the other is connected to the second adapter through at least one fourth connecting via. Both the third connecting via and the fourth connecting via penetrate the first interlayer insulation layer and the second interlayer insulation layer.
According to claim 3, the orthographic projections of the third adapter and the signal line segment on the substrate do not overlap, and one orthographic projection of the third adapter on the substrate is located between two adjacent orthographic projections of the signal line segment on the substrate. For two adjacent signal segments and a connecting electrode for connecting them, the third connecting portion of the connecting electrode has a first end and a second end disposed opposite to each other along its extending direction; one signal segment has a third end connected to the first end of the third connecting portion via the first connecting portion; and the other signal segment has a fourth end connected to the second end of the third connecting portion via the second connecting portion. The orthographic projection of the first end on the substrate is wider the closer it is to the orthographic projection of the third end on the substrate; the orthographic projection of the second end on the substrate is wider the closer it is to the orthographic projection of the fourth end on the substrate; the orthographic projection of the third end on the substrate is wider the closer it is to the orthographic projection of the first end on the substrate; and the orthographic projection of the fourth end on the substrate is wider the closer it is to the orthographic projection of the second end on the substrate.
According to claim 4, the orthographic projection of the first connecting via for connecting the third adapter and the first adapter on the substrate is covered by the orthographic projection of the first end on the substrate; the orthographic projection of the second connecting via for connecting the third adapter and the second adapter on the substrate is covered by the orthographic projection of the second end on the substrate. The orthographic projection of the third connecting via for connecting the signal line segment and the first adapter on the substrate is covered by the orthographic projection of the third end on the substrate; the orthographic projection of the fourth connecting via for connecting the signal line segment and the second adapter on the substrate is covered by the orthographic projection of the fourth end on the substrate. The orthographic projection of the first adapter on the substrate covers the orthographic projections of the first end and the third end on the substrate; the orthographic projection of the second adapter on the substrate covers the orthographic projections of the second end and the fourth end on the substrate.
According to the display substrate of claim 5, there are multiple first connection vias at the first end, and the multiple first connection vias are arranged in multiple columns, wherein the number of first connection vias in each column is positively correlated with the linewidth of the first end. The second end has multiple second connection vias, and the multiple second connection vias are arranged in multiple columns. The number of second connection vias in each column is positively correlated with the line width of the second end. The third connection vias located at the third end are multiple, and the multiple third connection vias are arranged in multiple columns. The number of third connection vias in each column is positively correlated with the line width of the third end. The fourth connection vias located at the fourth end are multiple, and the multiple fourth connection vias are arranged in multiple columns. The number of fourth connection vias in each column is positively correlated with the line width of the fourth end.
According to claim 3, for two adjacent signal segments, one is connected to the third adapter through at least one fifth connecting via, and the other is connected to the third adapter through at least one sixth connecting via; both the fifth connecting via and the sixth connecting via penetrate the first interlayer insulating layer.
According to claim 7, for two adjacent signal segments and a connecting electrode for connecting them, the third connecting portion of the connecting electrode has a first end and a second end disposed opposite to each other along its extending direction; one signal segment has a third end connected to the first end of the third connecting portion via the first connecting portion; and the other signal segment has a fourth end connected to the second end of the third connecting portion via the second connecting portion; the orthographic projection of the first end on the substrate is wider the closer it is to the orthographic projection of the third end on the substrate; the orthographic projection of the second end on the substrate is wider the closer it is to the orthographic projection of the fourth end on the substrate. The orthographic projection of the first end on the substrate covers the orthographic projection of the third end on the substrate; the orthographic projection of the second end on the substrate covers the orthographic projection of the fourth end on the substrate.
According to claim 8, the display substrate wherein the fifth connection via is projected onto the substrate and is located within the area defined by the projected projections of the first connection via and the third connection via onto the substrate. The sixth connection via is projected onto the substrate and is located within the area defined by the projections of the second and fourth connection vias onto the substrate.
According to claim 8, the display substrate includes a first extension portion and a second extension portion at the first end; and a third extension portion and the fourth extension portion at the second end. The orthographic projections of the first extension portion and the second extension portion on the substrate do not overlap with the orthographic projection of the third end portion on the substrate; the orthographic projections of the third extension portion and the fourth extension portion on the substrate do not overlap with the orthographic projection of the fourth end portion on the substrate. At least a portion of the first connecting via overlaps with the orthographic projection of the first extension portion on the substrate; at least a portion of the first connecting via overlaps with the orthographic projection of the second extension portion on the substrate. At least a portion of the second connecting via overlaps with the orthographic projection of the third extension on the substrate; at least a portion of the second connecting via overlaps with the orthographic projection of the fourth extension on the substrate.
According to claim 3, the display substrate further includes a fourth transition portion; the second transition portion is located between adjacent signal segments and is connected to the third transition portion through at least one seventh connection via; the seventh connection via penetrates the first interlayer insulating layer.
The display substrate according to any one of claims 1-11 further includes a redundant shift register located in the peripheral region; The redundant shift register includes: an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, and at least one pull-down sub-circuit. The input sub-circuit is configured to pre-charge the pull-up node in response to an input signal at the signal input terminal; the connection node between the input sub-circuit, the output sub-circuit, and the pull-down sub-circuit; The output sub-circuit is configured to output a clock signal through a signal output terminal in response to the potential of the pull-up node; The output sub-circuit is configured to output a clock signal through a cascaded signal terminal in response to the potential of the pull-up node. The pull-down control subcircuit is configured to respond to the power supply voltage and control the potential of the pull-down node by the power supply voltage; one of the pull-down control subcircuits connects one of the pull-down subcircuits and one of the pull-down subcircuits, and the connection node between the two is the pull-down node; The pull-down sub-circuit is configured to pull down the potential of the pull-up node by a non-operating level signal in response to the potential of the pull-up node.
According to claim 12, the display substrate, wherein the output sub-circuit comprises: a third transistor and a storage capacitor; The first end of the storage capacitor is connected to the gate of the third transistor, and the second end of the storage capacitor is connected to the drain of the third transistor; at least one of the source and drain of the third transistor is connected to the frame enable signal line.
According to claim 12, the display substrate, wherein the output sub-circuit comprises: a third transistor and a storage capacitor; The first end of the storage capacitor is connected to the gate of the third transistor, and the second end of the storage capacitor is connected to the drain of the third transistor; at least one of the source and drain of the third transistor is connected to the first tip structure, and the frame enable signal line is connected to the second tip structure. The tip of the first tip structure is opposite to the tip of the second tip structure; or, The first tip structure includes a first body portion and at least one first tip portion connected to one side of the first body portion extending in the direction of extension; the second tip structure includes a second body portion and at least one second tip portion connected to one side of the second body portion extending in the direction of extension; the first tip portion and the second tip portion are opposite to each other.
According to claim 12, the display substrate, wherein the pull-down control sub-circuit includes a fifth transistor and a ninth transistor; the pull-down sub-circuit includes a sixth transistor and an eighth transistor; The gate of the fifth transistor is connected to the drain of the ninth transistor and the source of the eighth transistor. The source of the fifth transistor is connected to the power supply voltage terminal and the gate of the ninth transistor. The drain of the fifth transistor is connected to the pull-down node. The gate of the sixth transistor is connected to the gate of the eighth transistor and the pull-up node, and the source of the sixth transistor is connected to the pull-down node; the drains of the sixth transistor and the eighth transistor are both connected to a non-operating level signal terminal. The frame enable signal line is connected to the source of the eighth transistor, and/or the frame enable signal line is connected to the gate of the sixth transistor.
According to claim 12, the display substrate, wherein the pull-down control sub-circuit includes a fifth transistor and a ninth transistor; the pull-down sub-circuit includes a sixth transistor and an eighth transistor; The gate of the fifth transistor is connected to the drain of the ninth transistor and the source of the eighth transistor. The source of the fifth transistor is connected to the power supply voltage terminal and the gate of the ninth transistor. The drain of the fifth transistor is connected to the pull-down node. The gate of the sixth transistor is connected to the gate of the eighth transistor and the pull-up node, and the source of the sixth transistor is connected to the pull-down node; the drains of the sixth transistor and the eighth transistor are both connected to a non-operating level signal terminal. One of the source of the eighth transistor and the gate of the sixth transistor is connected to the first tip structure, and the frame enable signal line is connected to the second tip structure. The tip of the first tip structure is opposite to the tip of the second tip structure; or, The first tip structure includes a first body portion and at least one first tip portion connected to one side of the first body portion extending in the direction of extension; the second tip structure includes a second body portion and at least one second tip portion connected to one side of the second body portion extending in the direction of extension; the first tip portion and the second tip portion are opposite to each other.
The display substrate according to any one of claims 1-11 further includes a redundant clock signal line, wherein the frame enable signal line is connected to the redundant clock signal line.
A display device comprising a display substrate according to any one of claims 1-17.

Description

Display substrate and display device Technical Field This disclosure belongs to the field of display technology, specifically relating to a display substrate and a display device. Background Technology During the manufacturing process of TFT-LCD (Thin Film Transistor Liquid Crystal Display), electrostatic charges accumulate on the substrate due to various factors such as equipment, power application during testing, and the external environment. When the charge on the substrate reaches a certain peak value, it triggers electrostatic discharge (ESD). This discharge typically generates a strong discharge current, which can potentially damage components in the circuitry, leading to display device malfunctions. In many current TFT-LCD products, gate drive electrodes are located in the peripheral area. These gate drive electrodes include multiple cascaded shift registers, with the signal input of the first shift register typically connected to the frame enable signal line. Because the frame enable signal line is singular and has few discharge paths, it is prone to ESD, which can burn out the via structure and GOA (Gate on Array) unit, causing abnormal screen display. Summary of the Invention The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a display substrate and a display device. This disclosure provides a display substrate, which includes: The substrate is divided into a display area and a peripheral area located on at least one side of the display area; A gate drive circuit and a frame enable signal line are disposed on the substrate, located in the peripheral region. The frame enable signal line is configured to provide a frame enable signal to at least one shift register in the gate drive circuit. The frame enable signal line includes at least two disconnected signal segments and a transition electrode connecting two adjacent signal segments; the transition electrode and the signal segments are located on different layers. The display substrate further includes: A first conductive layer is disposed on the substrate, and the gates of each thin-film transistor of the shift register are located in the first conductive layer; The first interlayer insulating layer is disposed on the side of the first conductive layer away from the substrate. The second conductive layer is disposed on the side of the first interlayer insulating layer away from the first conductive layer, and the source and drain of each thin film transistor of the shift register are located in the second conductive layer. The second interlayer insulating layer is disposed on the side of the second conductive layer that is opposite to the first interlayer insulating layer; The third conductive layer is disposed on the side of the second interlayer insulating layer away from the second conductive layer, and the common electrode of the pixel unit located in the display area is located in the third conductive layer. The adapter electrode includes a first adapter portion, a second adapter portion, and a third adapter portion; the first adapter portion and the second adapter portion are located in the third conductive layer, and the third adapter portion is located in the second conductive layer. The first adapter portion and the second adapter portion are respectively connected to the third adapter portion through at least one first connection via and at least one second connection via; both the first connection via and the second connection via penetrate the second interlayer insulating layer. The signal line segment is located in the first conductive layer. For two adjacent signal line segments, one is connected to the first adapter through at least one third connecting via, and the other is connected to the second adapter through at least one fourth connecting via. Both the third connecting via and the fourth connecting via penetrate the first interlayer insulation layer and the second interlayer insulation layer. Wherein, the orthographic projections of the third adapter and the signal line segment on the substrate do not overlap, and the orthographic projection of one of the third adapters on the substrate is located between two adjacent orthographic projections of the signal line segment on the substrate. For two adjacent signal segments and a connecting electrode for connecting them, the third connecting portion of the connecting electrode has a first end and a second end disposed opposite to each other along its extending direction; one signal segment has a third end connected to the first end of the third connecting portion via the first connecting portion; and the other signal segment has a fourth end connected to the second end of the third connecting portion via the second connecting portion. The orthographic projection of the first end on the substrate is wider the closer it is to the orthographic projection of the third end on the substrate; the orthographic projection of