WO-2026092052-A1 - ARRAY SUBSTRATE AND DISPLAY DEVICE

WO2026092052A1WO 2026092052 A1WO2026092052 A1WO 2026092052A1WO-2026092052-A1

Abstract

An array substrate and a display device. The array substrate comprises a base substrate (1), a driver circuit layer assembly (2), a first electrode (3) and second electrodes (6), wherein the base substrate, the driver circuit layer assembly, the first electrode and the second electrodes are stacked. The driver circuit layer assembly (2) comprises a gate layer (21) and a conductor layer (24), and the gate layer (21) comprises a gate (211) and gate lines (212) extending in a first direction (X). The conductor layer (24) comprises data lines (241) and signal wires (244), the data lines and the signal wires extend in a second direction (Y), every two adjacent gate lines (212) form a gate line group (212Z), and a plurality of data lines (241) intersect with a plurality of gate line groups (212Z) to define a display area (AA) into a plurality of pixel areas (PXQ), and the driver circuit layer assembly (2) comprises first transistors (T1) and second transistors (T2). Every two adjacent second electrodes (6) are a first pixel electrode (6a) and a second pixel electrode (6b), the first pixel electrode (6a) comprises a first electrode portion (6a1) and a first lead portion (6a2) connected to each other, the second pixel electrode (6b) comprises a second electrode portion (6b1) and a second lead portion (6b2) connected to each other, the first lead portion (6a2) is connected to the corresponding first transistor (T1), the first transistor (T1) and the first electrode portion (6a1) are located in the same pixel column (PXL), the second lead portion (6b2) is connected to the corresponding second transistor (T2), and the second electrode portion (6b1) and the second transistor (T2) are respectively located in adjacent pixel columns (PXL). The orthographic projections of the second lead portions (6b2) on the base substrate (1) obliquely intersect with the orthographic projections of the signal wires (244) on the base substrate (1).

Inventors

GUO, JIANDONG
WU, Zhongshan
CHEN, JUNMING
ZHU, YUANYUAN
HE, DAFANG

Assignees

京东方科技集团股份有限公司
重庆京东方光电科技有限公司

Dates

Publication Date: 20260507
Application Date: 20250930
Priority Date: 20241101

Claims (20)

An array substrate has a display area and a non-display area, the non-display area including a fan-out area and a bonding area, wherein the array substrate includes: Substrate; A driving circuit layer group is disposed on one side of the substrate. The driving circuit layer group includes a gate layer and a conductor layer. The gate layer includes a gate and a gate line, and the gate line extends along a first direction. The conductor layer includes data lines and signal lines, and the data lines and signal lines extend along a second direction. Two adjacent gate lines form a gate line group. Multiple data lines and multiple gate line groups are intersected to define the display area as multiple pixel areas. The second direction intersects with the first direction. The driving circuit layer group includes multiple transistors, and the multiple transistors include a first transistor and a second transistor. A first electrode and a second electrode are disposed on the side of the driving circuit layer group away from the substrate. A second insulating layer is disposed between the second electrode and the first electrode. Two adjacent second electrodes are a first pixel electrode and a second pixel electrode. The first pixel electrode includes a first electrode portion and a first lead portion connected to each other. The second pixel electrode includes a second electrode portion and a second lead portion connected to each other. The first lead portion is connected to the first transistor. The first transistor and the first electrode portion are located in the same pixel column. The second lead portion is connected to the second transistor. The second electrode portion and the second transistor are located in adjacent pixel columns. The orthographic projection of the second lead portion on the substrate is obliquely intersected with the orthographic projection of the signal trace on the substrate.
According to claim 1, the array substrate further includes a conductive auxiliary layer, the conductive auxiliary layer including a first auxiliary trace, the first auxiliary trace being electrically connected to the first electrode; the orthographic projection of the first auxiliary trace on the substrate does not overlap with the orthographic projections of the first lead portion and the second lead portion on the substrate.
According to the array substrate of claim 2, the orthographic projection of the second electrode on the substrate near the corner of the first auxiliary trace overlaps with the orthographic projection of the first auxiliary trace on the substrate, and the other part of the orthographic projection of the second electrode on the substrate does not overlap with the orthographic projection of the first auxiliary trace on the substrate.
According to claim 2, the array substrate, wherein the first auxiliary trace extends along the second direction, and the orthographic projection of the first auxiliary trace on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.
According to claim 2, the array substrate further comprises: A spacer portion is disposed on the side of the second insulating layer away from the substrate, and the orthographic projection of the spacer portion on the substrate does not overlap with the orthographic projection of the first auxiliary trace on the substrate.
According to claim 2, the array substrate, wherein the first electrode portion and the second electrode portion are located in the same pixel region.
According to the array substrate of claim 6, the three pixel regions arranged along the first direction constitute a group, and a first auxiliary trace is provided in a group of pixel regions, or a first auxiliary trace is provided between two adjacent groups of pixel regions.
According to the array substrate of claim 7, the conductive auxiliary layer further includes a third auxiliary trace, the orthographic projection of the third auxiliary trace on the substrate is located between the orthographic projections of two adjacent second electrodes on the substrate, the third auxiliary trace is disconnected, and the virtual extension line of the third auxiliary trace intersects with the second lead portion.
According to the array substrate of claim 1, in the second direction, the first transistor and the second transistor are each located on opposite sides of the pixel region.
According to claim 9, the array substrate comprises multiple transistor groups, each transistor group comprises two transistors, the two transistors in the same group are located between two adjacent gate lines in the same group, the two transistors in the same group are connected to opposite sides of the same data line in the first direction and are staggered in the second direction; the two gates of the two transistors in the same group are connected one-to-one to two adjacent gate lines in the same group.
According to claim 9, the array substrate wherein the gate lines are configured as straight lines extending along the first direction.
According to claim 7, the array substrate, wherein the data line and the signal trace are configured as strips extending along the second direction, a portion of the signal trace is located within the pixel region, the driving circuit layer group includes a first insulating layer, the first insulating layer is located between the conductor layer and the first electrode, the first electrode is connected to the signal trace through a third via on the first insulating layer, and the orthographic projection of the third via on the substrate is located between the orthographic projections of two adjacent transistors on the substrate.
According to the array substrate of claim 12, the orthographic projection of the second lead portion on the substrate overlaps with the orthographic projection of the signal trace on the substrate, and the orthographic projection of the first lead portion on the substrate does not overlap with the orthographic projection of the signal trace on the substrate.
According to any one of claims 1 to 13, the array substrate comprises a third segment and a fourth segment, the third segment being connected to the second electrode portion, the fourth segment being connected to one end of the third segment away from the second electrode portion, the fourth segment being connected to the second transistor, the fourth segment extending along the first direction, the third segment extending along a third direction, the third direction intersecting the first direction, the third direction intersecting the second direction, and the orthographic projection of the third segment on the substrate being obliquely intersecting the orthographic projection of the signal trace on the substrate.
According to claim 14, the array substrate wherein the included angle between the third segment and the fourth segment is greater than or equal to 135° and less than 180°.
According to the array substrate of claim 14, a portion of the second pixel electrodes of the plurality of second pixel electrodes are third sub-pixel electrodes, a portion of the second pixel electrodes of the plurality of second pixel electrodes are fourth sub-pixel electrodes, the third sub-pixel electrodes and the fourth sub-pixel electrodes are located in adjacent pixel columns and adjacent pixel rows, such that the third sub-pixel electrodes and the fourth sub-pixel electrodes are arranged obliquely opposite each other.
According to the array substrate of claim 16, the orthographic projection of the second lead portion of the third sub-pixel electrode on the substrate and the orthographic projection of the second lead portion of the fourth sub-pixel electrode on the substrate are obliquely intersecting with the orthographic projection of the same signal trace on the substrate. The fourth segment of the third sub-pixel electrode and the fourth segment of the fourth sub-pixel electrode are located between two gate lines in the same group. The third segment of the third sub-pixel electrode and the third segment of the fourth sub-pixel electrode are opposite to and parallel to each other in a fourth direction, and the fourth direction is perpendicular to the third direction.
According to the array substrate of claim 16, the second electrode portion of the third sub-pixel electrode has a third edge line and a fourth edge line disposed opposite to each other, the third edge line intersecting the first direction, the fourth edge line intersecting the first direction, the third segment of the third sub-pixel electrode being closer to the third edge line relative to the fourth edge line, and the angle between the edge line of the third segment of the third sub-pixel electrode closer to the second electrode portion and the third edge line being an acute angle; The second lead portion of the third sub-pixel electrode further includes a fifth segment, which is connected between the third segment and the second electrode portion. The angle between the edge of the fifth segment connected to the third edge and the third edge is a right angle or an obtuse angle, and the angle between the fifth segment and the edge of the third segment near the second electrode portion is also a right angle or an obtuse angle.
According to the array substrate of claim 16 or 18, the second electrode portion of the fourth sub-pixel electrode has a third edge line and a fourth edge line disposed opposite to each other, the third edge line intersecting the first direction, the fourth edge line intersecting the first direction, the third segment of the fourth sub-pixel electrode being closer to the fourth edge line than the third edge line, and the angle between the edge line of the third segment of the fourth sub-pixel electrode closer to the second electrode portion and the fourth edge line being an obtuse angle.
According to the array substrate of claim 18, the third segment of the fourth sub-pixel electrode is connected to the edge line extending along the first direction of the second electrode portion, one side edge line of the third segment of the fourth sub-pixel electrode is connected to the second electrode portion, and the opposite side edge line of the third segment of the fourth sub-pixel electrode is connected to the second electrode portion through a straight edge line extending along the second direction; the fifth segment of the third sub-pixel electrode is connected to the edge line extending along the first direction of the second electrode portion.

Description

Array substrate and display device Cross-referencing This disclosure claims priority to patent application No. PCT/CN2024/129376, filed on November 1, 2024, entitled "Array Substrate and Display Device", the entire contents of which are incorporated herein by reference. Technical Field This disclosure relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology Liquid crystal displays (LCDs) are widely used in various display fields, such as homes, public places, offices, and personal electronic products. However, with the development of technology, current display products cannot meet the increasingly higher requirements of customers. It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention The purpose of this disclosure is to overcome the shortcomings of the prior art and provide an array substrate and a display device. According to one aspect of this disclosure, an array substrate is provided having a display area and a non-display area, the non-display area including a fan-out region and a bonding region, the array substrate comprising: Substrate; A driving circuit layer group is disposed on one side of the substrate. The driving circuit layer group includes a gate layer and a conductor layer. The gate layer includes a gate and a gate line, and the gate line extends along a first direction. The conductor layer includes data lines and signal lines, and the data lines and signal lines extend along a second direction. Two adjacent gate lines form a gate line group. Multiple data lines and multiple gate line groups are intersected to define the display area as multiple pixel areas. The second direction intersects with the first direction. The driving circuit layer group includes multiple transistors, and the multiple transistors include a first transistor and a second transistor. A first electrode and a second electrode are disposed on the side of the driving circuit layer group away from the substrate. A second insulating layer is disposed between the second electrode and the first electrode. Two adjacent second electrodes are a first pixel electrode and a second pixel electrode. The first pixel electrode includes a first electrode portion and a first lead portion connected to each other. The second pixel electrode includes a second electrode portion and a second lead portion connected to each other. The first lead portion is connected to the first transistor. The first transistor and the first electrode portion are located in the same pixel column. The second lead portion is connected to the second transistor. The second electrode portion and the second transistor are located in adjacent pixel columns. The orthographic projection of the second lead portion on the substrate is obliquely intersected with the orthographic projection of the signal trace on the substrate. In one exemplary embodiment of this disclosure, the array substrate further includes a conductive auxiliary layer, the conductive auxiliary layer including a first auxiliary trace, the first auxiliary trace being electrically connected to the first electrode; the orthographic projection of the first auxiliary trace on the substrate does not overlap with the orthographic projections of the first lead portion and the second lead portion on the substrate. In one exemplary embodiment of this disclosure, the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the first auxiliary trace near the corner of the first auxiliary trace on the substrate, while the other portions of the orthographic projection of the second electrode on the substrate do not overlap with the orthographic projection of the first auxiliary trace on the substrate. In one exemplary embodiment of this disclosure, the first auxiliary trace extends along the second direction, and the orthographic projection of the first auxiliary trace on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate. In one exemplary embodiment of this disclosure, the array substrate further includes: A spacer portion is disposed on the side of the second insulating layer away from the substrate, and the orthographic projection of the spacer portion on the substrate does not overlap with the orthographic projection of the first auxiliary trace on the substrate. In one exemplary embodiment of this disclosure, the first electrode portion and the second electrode portion are located within the same pixel region. In one exemplary embodiment of this disclosure, three pixel regions arranged along the first direction form a group, and a first auxiliary trace is provided in a group of pixel regions