WO-2026092144-A1 - METHOD FOR TESTING SINGLE EVENT EFFECTS IN SIP DEVICE

WO2026092144A1WO 2026092144 A1WO2026092144 A1WO 2026092144A1WO-2026092144-A1

Abstract

A method for testing single event effects in a SiP device. The method comprises: on the basis of depth information of a sensitive area of a SiP device, decapping or thinning the SiP device; on the basis of the structures and models of embedded chips of the SiP device, determining a sensitive module of each embedded chip therein, and performing irradiation test analysis on each sensitive module, so as to obtain single event effects test items for the SiP device; determining a test plan, and performing a targeted design on test software and hardware; injecting an error mode into the designed software and hardware to perform simulation verification, and if the simulation verification fails, modifying test procedures, and re-performing the simulation verification; performing a single-event test on each embedded chip; performing an irradiation test on the SiP device; and after the test is completed, uploading, saving and analyzing test data, and ending the test. The present method solves the problems of a ground test of SiP single event effects being inaccurate, and the test method and a test apparatus being limited to specific models.

Inventors

MEI, Bo
WEI, Zhichao
LV, He
ZHANG, HAIMING
ZHANG, HONGWEI
CAO, Shuang
XUE, Yuxiong
CAO, Rongxing

Assignees

中国空间技术研究院

Dates

Publication Date: 20260507
Application Date: 20251015
Priority Date: 20241029

Claims (15)

A method for testing single-event effects in SiP devices, characterized by comprising: S1. Based on the depth information of the sensitive area of the SiP device, the SiP device is subjected to capping or thinning treatment. S2. Analyze each embedded chip of the SiP device to obtain the single-event effect test items of the SiP device; S3. The test system for the single-event effect test of SiP devices includes hardware and software components. The hardware component includes the DUT test board and control board, and the software component includes the host computer software unit and the slave computer software unit. S4. Simulate and verify the injection of errors into the hardware and software components. If the simulation verification fails, modify the test system and repeat the simulation verification. If the simulation verification passes, proceed to S5. S5. Perform single-event tests on each embedded chip of the SiP device. The DUT test board is connected to both the embedded chip of the SiP device and the control board, serving as the interface between the SiP device and the control board. The control board sends control commands to the embedded chip of the SiP device, configures and reads the configuration code stream of the embedded chip of the SiP device, analyzes and records the single-event flip information based on the configuration code stream. The lower-level software unit powers on the control board, monitors and records the operating current data of the SiP device. The control board and the lower-level software unit send the recorded data to the upper-level software unit for display and storage. S6. Conduct an overall irradiation test on the SiP device.
A single-event effect testing method for SiP devices according to claim 1, characterized in that: the embedded chips of the SiP device include: a field-programmable gate array (FPGA) chip, a PROM chip, and an analog-to-digital converter (ADC) chip.
A single-event effect testing method for SiP devices according to claim 1, characterized in that: the DUT test board meets the functions of self-starting power-on operation of the SiP device during testing, BPI and JTAG program configuration, and also provides a SelectMAP interface for communication between the SiP device and the control board, specifically: When designing the power-on circuit, two LTM4644 chips were selected as DC-DC power chips to output 8 voltage and current channels; The JTAG and BPI interfaces are brought out to load the configuration program of the SiP device, and the RS485 interface circuit is brought out to complete the data transmission between the DUT test board and the host computer, which meets the self-starting test requirement during single-chip testing. The interface between the DUT test board and the SiP device, as well as the SelectMAP interface with the control board, are brought out. The SelectMAP interface with the control board is designed as a universal FMC interface. The control board uses this interface to remotely control and monitor the DUT test board in real time, meeting the requirements of dual-chip testing.
A single-event effect testing method for SiP devices according to claim 3, characterized in that: a main control FPGA chip is provided in the control board, and the main control FPGA chip is used to realize remote control of the DUT test board and data communication with the host computer, specifically: The control board should bring out at least two general-purpose banks of the main control FPGA chip to establish a data transmission channel with the FMC interface of the DUT test board; The main control FPGA chip of the control board needs to be connected to an external storage chip to store the power-on configuration program and test data of the DUT test board; When the control board interacts with the host computer, a serial port channel needs to be reserved.
A single-event effect testing method for SiP devices according to claim 3, characterized in that: the host computer software unit is a remote control terminal developed based on LabVIEW, which receives, displays, and saves the recorded data from the control board and the slave computer software unit, specifically: Real-time display of single-event upset and single-event failure information of the device under test; The curves of the working current of each SiP circuit changing with time under irradiation are monitored in real time to determine whether single-event lock-up occurs, and then all test results are saved in txt format.
According to claim 2, a single-event effect testing method for SiP devices is characterized in that: the lower-level software unit includes single-event test programs for FPGA module, PROM module and ADC module, which are used to power on the main control FPGA chip of the control board, monitor and record the operating current of FPGA chip, PROM chip and ADC chip and send the recorded results to the upper-level software unit when performing single-event tests on FPGA chip, PROM chip and ADC chip respectively.
A method for single-event effect testing of SiP devices according to claim 6, characterized in that: when performing single-event testing on the FPGA chip of the SiP device: The power supply parameters of the main FPGA chip on the control board are set by the FPGA module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the FPGA chip of the SiP device is powered on by the DUT test board. The control board sends control commands to the FPGA chip of the SiP device, loads the configuration code stream onto the FPGA chip of the SiP device, and then turns on the beam to conduct the irradiation test. The FPGA module in the lower-level software unit monitors the operating current of the FPGA chip of the SiP device in real time. When the operating current exceeds 1.5 times its operating current during irradiation, it is determined that a single-event lock has occurred. At this time, the FPGA chip of the SiP device is powered off and restarted, and the error information is recorded. The control board reads the program configuration code stream of the FPGA chip of the SiP device in real time through the SelectMAP interface and compares it with the initially written configuration code stream. If they are inconsistent, it determines that a single event flip has occurred and records the number of single event flips and the frame address. Finally, all test results were uploaded to the host computer software unit.
A single-event effect testing method for SiP devices according to claim 7, characterized in that: when performing single-event testing on the PROM chip or ADC chip of the SiP device: The power supply parameters of the main FPGA chip on the control board are set by the PROM module or ADC module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the PROM chip or ADC chip of the SiP device is powered on by the DUT test board. The main control FPGA chip on the control board writes the configuration code stream into the ADC chip or PROM chip of the SiP device to put it into normal working state and start the irradiation test; during the irradiation process, the PROM module or ADC module in the lower computer software unit monitors the working current of the PROM chip or ADC chip in real time to determine whether single-event lock occurs. During the irradiation process, the control board reads the configuration code stream of the ADC chip or PROM chip and compares it with the initial configuration code stream to obtain the single-event flip results of the PROM chip or ADC chip, as well as the single-event transient test data of the ADC chip. All test data are uploaded to the host computer software unit for storage and display.
According to claim 1, a method for testing the single-event effect of a SiP device is characterized in that: when conducting an overall irradiation test on the SiP device, if the beam spot cannot completely cover the SiP device, then the embedded chips are irradiated one by one.
A single-event effect testing system for SiP devices, characterized in that it includes: a hardware part and a software part, the hardware part including a DUT test board and a control board, and the software part including a host computer software unit and a slave computer software unit; The DUT test board is used to power on the SiP device and connect the embedded chip of the SiP device to the control board, serving as the interface between the SiP device and the control board. The control board connects to the embedded chip of the SiP device through the DUT test board and sends control commands to it. It configures and reads the configuration code stream of the embedded chip of the SiP device, analyzes and records the single-particle flip information accordingly, and can communicate with the host computer. The lower-level software unit is located in the lower-level machine. On the one hand, it connects to the control board to power it on. On the other hand, it includes single-event test programs developed for FPGA, PROM and ADC chips in SiP devices, monitors and records the operating current data of SiP devices and uploads the test data to the upper-level software unit. The host computer software unit is located in the host computer, receives the recorded data from the control board and the slave computer software unit, and monitors the single-event test of the SiP device.
A single-event effect testing system for SiP devices according to claim 10, characterized in that: the DUT test board satisfies the functions of self-starting power-on operation of the SiP device during testing, BPI and JTAG program configuration, and provides a SelectMAP interface for communication between the SiP device and the control board, specifically: Two LTM4644 chips were selected as DC-DC power supply chips, with 8 voltage and current outputs for the self-starting power-on of SiP devices. The JTAG and BPI interfaces are brought out to load the configuration program of the SiP device, and the RS485 interface circuit is brought out to complete the data transmission between the DUT test board and the host computer, so as to meet the self-starting test requirements during single-chip testing. The interface between the DUT test board and the SiP device, as well as the SelectMAP interface with the control board, are brought out. The SelectMAP interface with the control board is designed as a universal FMC interface. The control board uses this interface to remotely control and monitor the DUT test board in real time to meet the needs of dual-chip testing.
A single-event effect testing system for SiP devices according to claim 11, characterized in that: a main control FPGA chip is provided in the control board, which enables remote control of the DUT test board and data communication with the host computer software; the control board has at least two general-purpose banks of the main control FPGA chip connected to establish a data transmission channel with the FMC interface of the DUT test board; an external storage chip is connected to the main control FPGA chip of the control board to store the power-on configuration program and test data of the DUT test board; a serial port channel is reserved when the control board interacts with the host computer.
A single-event effect testing system for SiP devices according to claim 10 is characterized in that: the host computer software unit is developed based on LabVIEW and can display the single-event upset and single-event interruption information of the sensitive module of the SiP device under test in real time; it can monitor the curves of the working current of each SiP under irradiation environment over time in real time, determine whether single-event lock-up occurs, and then save all test results in txt format.
A single-event effect testing system for SiP devices according to claim 10, characterized in that: when performing single-event testing on the FPGA chip of the SiP device: The power supply parameters of the main FPGA chip on the control board are set by the FPGA module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the FPGA chip of the SiP device is powered on by the DUT test board. The control board sends control commands to the FPGA chip of the SiP device, loads the configuration code stream onto the FPGA chip of the SiP device, and then turns on the beam to conduct the irradiation test. The FPGA module in the lower-level software unit monitors the operating current of the FPGA chip of the SiP device in real time. When the operating current exceeds 1.5 times its operating current during irradiation, it is determined that a single-event lock has occurred. At this time, the FPGA chip of the SiP device is powered off and restarted, and the error information is recorded. The control board reads the program configuration code stream of the FPGA chip of the SiP device in real time through the SelectMAP interface and compares it with the initially written configuration code stream. If they are inconsistent, it determines that a single event flip has occurred and records the number of single event flips and the frame address. Finally, all test results were uploaded to the host computer software unit.
A single-event effect testing system for SiP devices according to claim 10, characterized in that: when performing single-event testing on a PROM chip or an ADC chip: The power supply parameters of the main FPGA chip on the control board are set by the PROM module or ADC module in the lower-level software unit, and the main FPGA chip on the control board is powered on; the PROM chip or ADC chip of the SiP device is powered on by the DUT test board. The main control FPGA chip on the control board writes the configuration code stream into the ADC chip or PROM chip of the SiP device to put it into normal working state and start the irradiation test; during the irradiation process, the PROM module or ADC module in the lower computer software unit monitors the working current of the PROM chip or ADC chip in real time to determine whether single-event lock occurs. During the irradiation process, the control board reads the configuration code stream of the ADC chip or PROM chip and compares it with the initial configuration code stream to obtain the single-event flip results of the PROM chip or ADC chip, as well as the single-event transient test data of the ADC chip. All test data are uploaded to the host computer software unit for storage and display.

Description

A method for testing single-event effects in SiP devices This application claims priority to Chinese Patent Application No. 2024115218192, filed on October 29, 2024, entitled "A General Method for Single-Event Effect Testing of SiP Devices", the entire contents of which are incorporated herein by reference. Technical Field This invention relates to a method for testing single-event effects in SiP devices, belonging to the field of single-event testing technology. Background Technology Since the beginning of the 21st century, with the rapid development of aerospace technology, higher demands have been placed on the integration and miniaturization of spaceborne computer electronic systems. From a system integration perspective, System-in-Package (SiP) is an effective method to promote the miniaturization, high performance, low power consumption, and high reliability of electronic systems. It uses three-dimensional stacked packaging technology to encapsulate multiple bare chips of electronic components with different functions into a microsystem, mainly including Field-Programmable Gate Arrays (FPGAs), memory, Analog-to-Digital Converters (ADCs), and Digital Signal Processors (DSPs). Due to its characteristics of miniaturization, high performance, low power consumption, low cost, short development cycle, and rapid iteration, it has become the primary choice for spaceborne computers. In space, due to space radiation, when a single high-energy particle enters a SiP device, it generates a large number of electron-hole pairs near the particle's track. These electron-hole pairs are collected by the sensitive modules within the SiP, leading to device malfunction or failure, i.e., the single-event effect (SEE). Therefore, aerospace-grade SiPs require ground-based radiation hardening testing and evaluation. Currently, in the field of single-event effect testing for SiP devices, there is no universal method for testing single-event effects in SiP devices due to the different chips packaged in different models of SiP devices. Summary of the Invention The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a single-event effect testing method for SiP devices, which solves the problems of inaccurate ground-based single-event effect testing of SiP devices and the limitation of testing methods and testing devices to specific models. The technical solution of this invention is: Firstly, a method for testing single-event effects in SiP devices is provided, including: S1. Based on the depth information of the sensitive area of the SiP device, the SiP device is subjected to capping or thinning treatment. S2. Analyze each embedded chip of the SiP device to obtain the single-event effect test items of the SiP device; S3. The test system for the single-event effect test of SiP devices includes hardware and software components. The hardware component includes the DUT test board and control board, and the software component includes the host computer software unit and the slave computer software unit. S4. Simulate and verify the injection of errors into the hardware and software components. If the simulation verification fails, modify the test system and repeat the simulation verification. If the simulation verification passes, proceed to S5. S5. Perform single-event experiments on each embedded chip of the SiP device. The DUT test board is connected to both the embedded chip of the SiP device and the control board, serving as the interface between the SiP device and the control board. The control board connects to the embedded chip of the SiP device and sends control commands to it, configures and reads the configuration code stream of the embedded chip of the SiP device, and analyzes and records the single-event flip information accordingly. The lower-level software unit connects to the control board to power it on, and monitors and records the operating current data of the SiP device. The control board and the lower-level software unit send the recorded data to the upper-level software unit for display and storage. S6. Conduct an overall irradiation test on the SiP device. Preferably, the embedded chips in the SiP device include: a field-programmable gate array (FPGA) chip, a PROM chip, and an analog-to-digital converter (ADC) chip. Preferably, the DUT test board meets the requirements for self-starting power-on operation of SiP devices during testing, BPI and JTAG program configuration functions, and also provides a SelectMAP interface for communication between SiP devices and the control board. Specifically: When designing the power-on circuit, two LTM4644 chips were selected as DC-DC power chips to output 8 voltage and current channels; The JTAG and BPI interfaces are brought out to load the configuration program of the SiP device, and the RS485 interface circuit is brought out to complete the data transmission between the DUT test board and the host computer, which meets the