WO-2026093102-A1 - DYNAMIC FREQUENCY ADJUSTMENT IN MULTI-CHIPLET ARRANGEMENT

Abstract

The present disclosure relates generally to multi-processor arrangements and, more particularly, to dynamic frequency adjustments for multi-chiplet arrangements.

Inventors

• BHARASWADKAR, ANIKET VINAYAK
• GOEL, DEEPAK

Assignees

• ARM LIMITED

Dates

Publication Date

20260507

Application Date

20251022

Priority Date

20241029

Claims (20)

1. 1. An apparatus, comprising: a first chiplet comprising a first plurality of processing elements interconnected via a first intra-chiplet interconnect; a second chiplet comprising a second plurality of processing elements interconnected via a second intra-chiplet interconnect; and an inter-chiplet interconnect to electronically couple at least the first chiplet to at least the second chiplet; wherein the first chiplet comprises one or more storage buffers having a capacity sufficient to losslessly receive a plurality of signal packets from the second chiplet for an allowable difference in a first clock frequency for the first intra-chiplet interconnect and a second clock frequency for the second intra-chiplet interconnect.
2. 2. The apparatus of claim 1 , wherein at least one of the first clock frequency and the second clock frequency is independently adjustable.
3. 3. The apparatus of any of the preceding claims, wherein the inter-chiplet interconnect operates at a fixed clock frequency with fixed data flow characteristics.
4. 4. The apparatus of any of the preceding claims, further comprising: a plurality of chiplets including the first and second chiplets, wherein respective chiplets of the plurality of chiplets comprise multiple processing elements interconnected via at least one of a mesh-type, star-type, or ring-type intra-chiplet interconnect. 42 P08434W001
5. 5. The apparatus of any of the preceding claims, wherein individual intra- chiplet interconnects for the respective plurality of chiplets operate at a voltage and/or a frequency selected independent of any other intra-ch iplet interconnect for any other chiplet of the plurality of chiplets.
6. 6. The apparatus of any of the preceding claims, wherein, for the inter- chiplet interconnect, individual chiplets of the plurality of chiplets are bi-directionally interconnected with at least one other chiplet of the plurality of chiplets via a plurality of links, wherein the plurality of links are individually capable of transmitting and/or receiving a plurality of signal packets.
7. 7. The apparatus of any of the preceding claims, wherein the plurality of chiplets respectively comprise a plurality of storage buffers corresponding to the plurality of links, wherein the plurality of storage buffers respectively have capacities sufficient to losslessly receive signal packets via the plurality of links.
8. 8. The apparatus of any of the preceding claim, wherein, for the plurality of chiplets, the plurality of storage buffers have respective capacities implemented based, at least in part, on flit-based inter-chiplet interconnect protocol-level credit characteristics for an allowable range of operating frequencies for individual intra- chiplet interconnects for the respective plurality of chiplets.
9. 9. A method, comprising: transmitting, from a first chiplet of a plurality of chiplets to at least a second chiplet of the plurality of chiplets, a signal and/or signal packet indicative of an intention by the first chiplet to adjust a clock frequency for a first intra-ch iplet interconnect for the first chiplet; and 43 P08434W001 responsive at least in part to receiving the signal and/or signal packet indicative of the intention by the first chiplet to adjust the first intra-chiplet interconnect clock frequency, adjusting, at the at least the second chiplet, a signal packet generation and/or transmission rate in accordance with the indicated intention by the first chiplet to adjust the first intra-chiplet interconnect clock frequency.
10. 10. The method of claim 9, wherein the signal and/or signal packet indicative of the intention by the first chiplet to adjust the clock frequency for the first intra- chiplet interconnect comprises a signal and/or signal packet representative of a throttling rate parameter for an inter-chiplet interconnect, the method further comprising transmitting, from the second chiplet to the first chiplet via the inter- chiplet interconnect, a plurality of signal packets, including throttling, at the second chiplet, a signal packet generation rate in accordance with the throttling rate parameter.
11. 11 . The method of any of claims 9-10, wherein the throttling the signal packet generation rate at the second chiplet includes the second chiplet inserting bubbles into one or more links of a plurality of links of the inter-chiplet interconnect.
12. 12. The method of any of claims 9-11 , further comprising: responsive at least in part to detecting a thermal parameter exceeding the specified threshold and/or responsive at least in part to an adjustment of a workload parameter, determining, at the first chiplet, the adjustment of the operating clock frequency of the intra-chiplet interconnect of the first chiplet. P08434W001
13. 13. The method of any of claims 9-12, wherein the adjustment of the operating clock frequency of the intra-chiplet interconnect comprises a reduction in the operating clock frequency.
14. 14. The method of any of claims 9-13, wherein the transmitting, from the first chiplet of a plurality of chiplets to the at least the second chiplet of the plurality of chiplets, the signal and/or signal packet indicative of the intention by the first chiplet to adjust a clock frequency for the first intra-chiplet interconnect for the first chiplet further comprises transmitting, from the first chiplet of a plurality of chiplets to the at least the second chiplet of the plurality of chiplets, one or more signals and/or signal packets indicative of a specified future point in time at which the first chiplet is to adjust the clock frequency for the first intra-chiplet interconnect.
15. 15. The method of any of claim 9-14, further comprising adjusting, at individual chiplets of the plurality of chiplets, including the first and second chiplets, operating clock frequencies of respective intra-chiplet interconnects for the respective plurality of chiplets responsive at least in part to the signal and/or signal packet indicative of the intention by the first chiplet to adjust a clock frequency for the first intra-chiplet interconnect and further responsive to the one or more signals and/or signal packets indicative of the specified future point in time at which the first chiplet is to adjust the clock frequency for the first intra-chiplet interconnect.
16. 16. An apparatus, comprising: a first chiplet of a plurality of chiplets, wherein the first chiplet comprises a first plurality of processing elements interconnected via a first intra-chiplet interconnect; P08434W001 a second chiplet of the plurality of chiplets, wherein the second chiplet comprises a second plurality of processing elements interconnected via a second intra-chiplet interconnect; and an inter-chiplet interconnect to electronically couple at least the first chiplet to at least a second chiplet of the plurality of chiplets; wherein the first chiplet to transmit to at least the second chiplet, via one or more lanes of the inter- chiplet interconnect, a signal and/or signal packet indicative of an intention by the first chiplet to adjust a clock frequency for a first intra-chiplet interconnect for the first chiplet; and wherein the at least the second chiplet to adjust a signal packet generation and/or transmission rate in accordance with the indicated intention by the first chiplet to adjust the first intra-chiplet interconnect clock frequency.
17. 17. The apparatus of claim 16, wherein the signal and/or signal packet indicative of the intention by the first chiplet to adjust the clock frequency for the first intra-chiplet interconnect comprises a signal and/or signal packet representative of a throttling rate parameter for an inter-chiplet interconnect, wherein, to transmit to the first chiplet a plurality of signal packets, the at least the second chiplet to throttle a signal packet generation rate in accordance with the throttling rate parameter.
18. 18. The apparatus of any of claims 16-17, wherein the first chiplet to determine the adjustment of the operating clock frequency of the intra-chiplet interconnect of the first chiplet responsive at least in part to a detection of a thermal parameter exceeding the specified threshold and/or responsive at least in part to an adjustment of a workload parameter. P08434W001
19. 19. The apparatus of any of claims 16-18, wherein the signal and/or signal packet indicative of the intention by the first chiplet to adjust the clock frequency for the first intra-ch iplet interconnect further comprises one or more signals and/or signal packets indicative of a specified future point in time at which the first chiplet is to adjust the clock frequency for the first intra-chi plet interconnect.
20. 20. The apparatus of any of claims 16-19, wherein individual chiplets of the plurality of chiplets, including the first and second chiplets, are to adjust operating clock frequencies of respective intra-ch iplet interconnects responsive at least in part to the signal and/or signal packet indicative of the intention by the first chiplet to adjust a clock frequency for the first intra-ch iplet interconnect and further responsive to the one or more signals and/or signal packets indicative of the specified future point in time at which the first chiplet is to adjust the clock frequency for the first intra-chiplet interconnect.

Description

P08434W001 DYNAMIC FREQUENCY ADJUSTMENT IN MULTI-CHIPLET ARRANGEMENT BACKGROUND Field: [0001] The present disclosure relates generally to multi-processor arrangements and, more particularly, to dynamic frequency adjustments for multi- chiplet arrangements. Information: [0002] Integrated circuit devices, such as processors, for example, may be found in a wide range of electronic device types. Computing devices, for example, may include integrated circuit devices, such as processors, to process signals and/or states representative of diverse content types for a variety of purposes. Further, signal and/or state processing techniques continue to evolve. Some computing devices, for example, may include one or more Systems on a Chip (SoC)-type components comprising multi-chiplet arrangements, wherein individual chiplets may include multiple processing cores and/or other circuit types, for example. P08434W001 BRIEF DESCRIPTION OF THE DRAWINGS [0003] Claimed subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, both as to organization and/or method of operation, together with objects, features, and/or advantages thereof, it may best be understood by reference to the following detailed description if read with the accompanying drawings in which: [0004] FIG. 1 is a schematic block diagram depicting an example processing core including multiple processing elements, in accordance with an embodiment; [0005] FIG. 2 is a schematic block diagram depicting an example chiplet comprising a plurality of processing cores, in accordance with an embodiment; [0006] FIG. 3 is a schematic block diagram depicting an example arrangement of chiplets including an inter-ch iplet interconnect, in accordance with an embodiment; [0007] FIG. 4 is a schematic block diagram depicting an example inter-chiplet interconnect interface for a chiplet, in accordance with an embodiment; [0008] FIG. 5 is a schematic block diagram depicting example buffers for an example inter-chiplet interconnect interface for a chiplet, in accordance with an embodiment; [0009] FIG. 6 is a flow diagram depicting an example process for adjusting a signal packet generation and/or transmission rate at a chiplet of a multi-chiplet arrangement, in accordance with an embodiment; P08434W001 [0010] FIG. 7 is a flow diagram depicting an example process for dynamic voltage and/or frequency scaling (DVFS) within a multi-chiplet arrangement, in accordance with an embodiment; and [0011] FIG. 8 is a schematic diagram illustrating an embodiment of an example computing device. [0012] Reference is made in the following detailed description to accompanying drawings, which form a part hereof, wherein like numerals may designate like parts throughout that are corresponding and/or analogous. It will be appreciated that the figures have not necessarily been drawn to scale, such as for simplicity and/or clarity of illustration. For example, dimensions of some aspects may be exaggerated relative to others. Further, it is to be understood that other embodiments may be utilized. Furthermore, structural and/or other changes may be made without departing from claimed subject matter. References throughout this specification to “claimed subject matter” refer to subject matter intended to be covered by one or more claims, or any portion thereof, and are not necessarily intended to refer to a complete claim set, to a particular combination of claim sets (e.g., method claims, apparatus claims, etc.), or to a particular claim. It should also be noted that directions and/or references, for example, such as up, down, top, bottom, and so on, may be used to facilitate discussion of drawings and are not intended to restrict application of claimed subject matter. Therefore, the following detailed description is not to be taken to limit claimed subject matter and/or equivalents. P08434W001 DETAILED DESCRIPTION [0014] References throughout this specification o one implementation, an implementation, one embodiment, an embodiment, and/or the like means that a particular feature, structure, characteristic, and/or the like described in relation to a particular implementation and/or embodiment is included in at least one implementation and/or embodiment of claimed subject matter. Thus, appearances of such phrases, for example, in various places throughout this specification are not necessarily intended to refer to the same implementation and/or embodiment or to any one particular implementation and/or embodiment. Furthermore, it is to be understood that particular features, structures, characteristics, and/or the like described are capable of being combined in various ways in one or more implementations and/or embodiments and, therefore, are within intended claim scope. In general, of course, as has always been the case for the specification of a patent application, these and other issues have a potential to vary in a particular context of usa