WO-2026094392-A1 - SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

WO2026094392A1WO 2026094392 A1WO2026094392 A1WO 2026094392A1WO-2026094392-A1

Abstract

The present invention addresses the problem of raising the breakdown voltage of a semiconductor device. This semiconductor device comprises a semiconductor substrate having an element region and an outer peripheral region. The semiconductor substrate comprises: an element p-type layer disposed in the element region; an outer peripheral p-type layer disposed in the outer peripheral region so as to surround the element region; an outer peripheral n-type layer disposed on the outer peripheral side of the outer peripheral p-type layer so as to be spaced apart from the outer peripheral p-type layer; and a breakdown voltage p-type layer located between the outer peripheral p-type layer and the outer peripheral n-type layer. The semiconductor device comprises: an interlayer insulating film disposed on a substrate upper surface; an upper electrode disposed in the element region; a specific electrode disposed in the outer peripheral region; a semi-insulating film disposed in a range from the upper electrode to the specific electrode; and a protective insulating film disposed on a surface of the semi-insulating film. The semi-insulating film is disposed continuously from the upper electrode to the specific electrode and covers a specific electrode corner part.

Inventors

MURASE RYOSUKE
ISHIKAWA EISUKE
MASE Suguru
KUNO TAKASHI

Assignees

株式会社デンソー

Dates

Publication Date: 20260507
Application Date: 20250825
Priority Date: 20241028

Claims (14)

A semiconductor device (1) comprising a semiconductor substrate (12) having an element region (20) and an outer peripheral region (40) arranged to surround the outer periphery of the element region, The aforementioned semiconductor substrate is A p-type element layer (36) is arranged within the element region and is located in a range that includes the upper surface (12u) of the semiconductor substrate, It is arranged within the outer peripheral region so as to surround the element region, and is arranged in a range including the upper surface of the substrate, and is adjacent to the element p-type layer (42), A pressure-resistant p-type layer (44) is arranged within the outer peripheral region, positioned further outward than the outer peripheral p-type layer, and in a range including the upper surface of the substrate, It is equipped with, The aforementioned semiconductor device is An interlayer insulating film (50) is disposed on the upper surface of the substrate in the element region and the outer peripheral region, Within the element region, the upper electrode (14) is located on the surface of the interlayer insulating film, A specific electrode (51, 52) is disposed on the surface of the interlayer insulating film within the outer peripheral region, A semi-insulating film (56) arranged in the range from the upper electrode to the specific electrode, the semi-insulating film covering a part of the upper electrode, at least a part of the specific electrode, and the pressure-resistant p-type layer, A protective insulating film (58) is disposed on the surface of the semi-insulating film within the region of the semi-insulating film, It is equipped with, The specified electrode has a specified electrode upper surface (51u, 52u) parallel to the upper surface of the substrate, a specified electrode side surface (51s, 52s) connecting the specified electrode upper surface and the surface of the interlayer insulating film, and a specified electrode corner portion (51c, 52c) connecting the specified electrode upper surface and the specified electrode side surface. The semi-insulating film is arranged continuously from the upper electrode to the specific electrode and covers the corner portion of the specific electrode. Semiconductor equipment.
The specified electrode is a first electrode (51) that is positioned on the surface of the interlayer insulating film within the region of the outer p-type layer and surrounds the upper electrode. The upper surface of the specified electrode is the upper surface of the first electrode (51u), The aforementioned specific electrode side surface is the first electrode side surface (51s) that connects the upper surface of the first electrode and the surface of the interlayer insulating film, The specified electrode corner is the first electrode corner (51c) that connects the upper surface of the first electrode and the side surface of the first electrode. The semiconductor device according to claim 1, wherein the semi-insulating film is continuously arranged from the upper electrode to the first electrode and covers the corner portion of the first electrode.
The first electrode further comprises a recess (51r) formed on the upper surface, The semiconductor device according to claim 2, wherein the semi-insulating film is disposed within the recess.
The semiconductor device according to claim 3, wherein, in a vertical upward view of the upper surface of the substrate, the recess is formed in a groove shape so as to surround the element region.
The semiconductor substrate is located within the peripheral region, and further comprises a peripheral n-type layer (46) which is located within the area including the upper surface of the substrate, and is spaced apart from the peripheral p-type layer and located further outward than the peripheral p-type layer. The pressure-resistant p-type layer (44) is located between the outer p-type layer and the outer n-type layer. The specified electrode is a second electrode (52) that is positioned on the surface of the interlayer insulating film within the region of the outer n-type layer and surrounds the upper electrode. The upper surface of the specified electrode is the upper surface of the second electrode (52u), The aforementioned specific electrode side surface is the second electrode side surface (52s) that connects the upper surface of the second electrode and the surface of the interlayer insulating film. The specified electrode corner is the second electrode corner (52c) that connects the upper surface of the second electrode and the side surface of the second electrode. The semiconductor device according to claim 1, wherein the semi-insulating film is continuously arranged from the upper electrode to the second electrode and covers the corner portion of the second electrode.
The second electrode further comprises a recess (52r) formed on the upper surface of the second electrode, The semiconductor device according to claim 5, wherein the semi-insulating film is disposed within the recess.
The semiconductor device according to claim 6, wherein, in a vertical upward view of the upper surface of the substrate, the recess is formed in a groove shape so as to surround the element region.
The semiconductor substrate is located within the peripheral region, and further comprises a peripheral n-type layer (46) which is located within the area including the upper surface of the substrate, and is spaced apart from the peripheral p-type layer and located further outward than the peripheral p-type layer. The pressure-resistant p-type layer (44) is located between the outer p-type layer and the outer n-type layer. The specified electrodes are a first electrode (51) disposed on the surface of the interlayer insulating film within the region of the outer p-type layer and surrounding the upper electrode, and a second electrode (52) disposed on the surface of the interlayer insulating film within the region of the outer n-type layer and surrounding the first electrode. The aforementioned specific electrode surfaces are the upper surface of the first electrode (51u) and the upper surface of the second electrode (52u). The specified electrode side surface is the first electrode side surface (51s) connecting the upper surface of the first electrode and the surface of the interlayer insulating film, and the second electrode side surface (52s) connecting the upper surface of the second electrode and the surface of the interlayer insulating film. The specified electrode corner portion is a first electrode corner portion (51c) connecting the upper surface of the first electrode and the side surface of the first electrode, and a second electrode corner portion (52c) connecting the upper surface of the second electrode and the side surface of the second electrode. The semi-insulating film is arranged continuously from the upper electrode to the second electrode and covers the corners of the first electrode and the second electrode. The semiconductor device according to claim 1.
The facility further comprises a recess (52r) formed on at least one of the upper surfaces of the first electrode and the upper surface of the second electrode, The semiconductor device according to claim 8, wherein the semi-insulating film is disposed within the recess.
The semiconductor device according to claim 9, wherein, in a vertical upward view of the upper surface of the substrate, the recess is formed in a groove shape so as to surround the element region.
The semi-insulating film end (56e), which is the central end of the element region of the semi-insulating film, is located within the region of the upper electrode. The protective insulating film end (58e), which is the central end of the element region of the protective insulating film, is located within the region of the upper electrode and within the region of the semi-insulating film. The semiconductor device according to claim 1, wherein the end of the semi-insulating film protrudes further toward the center of the element region than the end of the protective insulating film.
The protective insulating film has a protective insulating film upper surface (58u) parallel to the upper surface of the substrate, and a protective insulating film side surface (58s) connecting the protective insulating film upper surface and the surface of the semi-insulating film. The semiconductor device according to claim 11, wherein, in a cross-section passing through the center of the element region and perpendicular to the upper surface of the substrate, the side surface of the protective insulating film has a curved surface that is convex downward.
The aforementioned semi-insulating film has a laminated structure comprising a first layer (56_1) and a second layer (56_2) disposed on the upper surface of the first layer. The semiconductor device according to claim 1, wherein the electrical resistance of the first layer is lower than the electrical resistance of the second layer.
A method for manufacturing a semiconductor device (1), The semiconductor device comprises a semiconductor substrate (12) having an element region (20) and an outer peripheral region (40) arranged to surround the outer periphery of the element region. The aforementioned semiconductor substrate is A p-type element layer (36) is arranged within the element region and is located in a range that includes the upper surface of the semiconductor substrate, The outer peripheral region is arranged to surround the element region, and is located in a range including the upper surface of the substrate, and is in contact with the element p-type layer (42), A pressure-resistant p-type layer (44) is arranged within the outer peripheral region, positioned further outward than the outer peripheral p-type layer, and in a range including the upper surface of the substrate, It is equipped with, The aforementioned semiconductor device is An interlayer insulating film (50) is disposed on the upper surface of the substrate in the element region and on the upper surface of the substrate in the peripheral region, Within the element region, the upper electrode (14) is located on the surface of the interlayer insulating film, A specific electrode (51, 52) is disposed on the surface of the interlayer insulating film within the outer peripheral region, A semi-insulating film (56) is arranged in the range from the upper electrode to the specific electrode, A protective insulating film (58) is disposed on the surface of the semi-insulating film within the region of the semi-insulating film, It is equipped with, The aforementioned manufacturing method is The steps include: (S4) forming the semi-insulating film on the entire surface of the semiconductor substrate on which the upper electrode, the specific electrode, and the pressure-resistant p-type layer are formed; The steps include: (S5) forming the protective insulating film on the entire surface of the semi-insulating film, A step (S6) of forming a mask having an aperture corresponding to the element region, The steps include forming an opening in the protective insulating film using the mask (S7), The steps include: (S8) isotropically etching the semi-insulating film through the opening of the protective insulating film; Equipped with, A method for manufacturing a semiconductor device.

Description

Semiconductor device and method for manufacturing a semiconductor device (Cross-reference of related applications) This application is a related application to Japanese Patent Application No. 2024-189160, filed on 28 October 2024, and claims priority based on the said Japanese Patent Application. All contents of the said Japanese Patent Application are incorporated herein by reference as constituting this specification. The technologies disclosed herein relate to semiconductor devices and methods for manufacturing semiconductor devices. The semiconductor device disclosed in Japanese Patent Publication No. 2014-33108 has an element region on which a semiconductor element is provided, and an outer peripheral region provided around the element region. A pressure-resistant structure such as a resurfacing layer and a guard ring is provided within the outer peripheral region. An n-type semiconductor region is provided on the outer peripheral side of the pressure-resistant structure. Electrodes are arranged on the upper surface of the inner peripheral side of the pressure-resistant structure and on the upper surface of the n-type semiconductor region. The upper surfaces of the electrodes and the pressure-resistant structure are covered with a semi-insulating film. Furthermore, the upper surface of the semi-insulating film is sealed with a protective insulating film (e.g., resin). Since external charges are dissipated to the electrodes by the semi-insulating film, charge does not accumulate near the pressure-resistant structure. Because the bias in the electric field distribution near the pressure-resistant structure can be suppressed, it is possible to increase the pressure resistance of the semiconductor device. In configurations sealed with a protective insulating film, thermal stress causes expansion and contraction at the interface between the electrode and the semi-insulating film. As a result, if cracks occur in the semi-insulating film near the breakdown structure, it becomes difficult to dissipate the charge near the breakdown structure to the electrode. This can lead to charge accumulation near the breakdown structure, potentially reducing the breakdown voltage of the semiconductor device. The semiconductor device disclosed herein comprises a semiconductor substrate having an element region and an outer peripheral region arranged to surround the outer periphery of the element region. The semiconductor substrate comprises an element p-type layer disposed within the element region and in a region including the upper surface of the semiconductor substrate, an outer peripheral p-type layer disposed within the outer peripheral region so as to surround the element region and in a region including the upper surface of the substrate, and adjacent to the element p-type layer, and a breakdown voltage p-type layer disposed within the outer peripheral region, located on the outer peripheral side of the outer peripheral p-type layer, and in a region including the upper surface of the substrate. The semiconductor device comprises an interlayer insulating film disposed on the upper surface of the substrate in the element region and the outer peripheral region, an upper electrode disposed on the surface of the interlayer insulating film within the element region, a specific electrode disposed on the surface of the interlayer insulating film within the outer peripheral region, a semi-insulating film disposed in the range from the upper electrode to the specific electrode, covering a part of the upper electrode, at least a part of the specific electrode, and the breakdown voltage p-type layer, and a protective insulating film disposed on the surface of the semi-insulating film within the region of the semi-insulating film. The specific electrode has a specific electrode upper surface parallel to the substrate upper surface, a specific electrode side surface connecting the specific electrode upper surface and the surface of the interlayer insulating film, and a specific electrode corner connecting the specific electrode upper surface and the specific electrode side surface. The semi-insulating film is continuously arranged from the upper electrode to the specific electrode and covers the specific electrode corner. In this semiconductor device, a semi-insulating film is continuously arranged from the upper electrode to a specific electrode and also covers the corner of the specific electrode. The semi-insulating film covering the corner of the specific electrode is more prone to stress concentration than the semi-insulating film covering the breakdown p-type layer. Therefore, the corner of the specific electrode can be designated as a crack initiation point where cracks can preferentially occur in the semi-insulating film. This allows cracks to occur in the semi-insulating film at the corner of the specific electrode when thermal stress is generated in the semiconductor device. Consequently, the stress on the semi-insulating