WO-2026094400-A1 - SEMICONDUCTOR WAFER AND SEMICONDUCTOR APPARATUS

Abstract

The present invention reduces the on-resistance of a vertical device of a semiconductor apparatus that comprises an SiC substrate and an AlGaN layer and includes a vertical device. A contact layer 20 that is formed from an Al x Ga 1-x N layer that has an Al composition of x at which the electron affinity of Al x Ga 1-x N and the electron affinity of SiC are substantially the same is formed on an SiC substrate 10 without an AlN layer therebetween.

Inventors

• MIURA, YOSHINAO
• YAMADA, HISASHI
• Hirai, Hirohisa
• NAKAJIMA, AKIRA
• KOJIMA, KAZUTOSHI
• HARADA, SHINSUKE

Assignees

• 国立研究開発法人産業技術総合研究所

Dates

Publication Date

20260507

Application Date

20250827

Priority Date

20241031

Claims (11)

1. A first-conductivity type silicon carbide substrate and A first nitride semiconductor layer is provided on the silicon carbide substrate, and the first conductivity type is Al x Ga 1-x N (0.25 < x ≤ 0.5), A second nitride semiconductor layer is provided on the first nitride semiconductor layer, having the first conductivity type, Al y Ga 1-y N (0 ≤ y ≤ 1), A semiconductor wafer equipped with the following features.
2. In the semiconductor wafer according to claim 1, The product of the thickness (cm) of the first nitride semiconductor layer and the impurity concentration (/ cm³ ) of the first nitride semiconductor layer is 4.5 × 10¹⁴ (/ cm² ) or less.
3. In the semiconductor wafer according to claim 1, The carbon concentration in the second nitride semiconductor layer is on the order of 10¹⁶ (/ cm³ ) or less. The oxygen concentration within the second nitride semiconductor layer is on the order of 10¹⁶ (/ cm³ ) or less.
4. In the semiconductor wafer according to claim 1, The Al composition within the second nitride semiconductor layer increases from the interface between the second nitride semiconductor layer and the first nitride semiconductor layer toward the upper surface of the second nitride semiconductor layer.
5. In the semiconductor wafer according to claim 1, The semiconductor wafer is a wafer for forming a device that conducts electric current in the thickness direction.
6. In the semiconductor wafer according to claim 1, The silicon carbide substrate and the first nitride semiconductor layer form a heterointerface between silicon carbide and Al x Ga 1-x N.
7. In the semiconductor wafer according to claim 1, The impurity concentration of the first nitride semiconductor layer is greater than the impurity concentration of the second nitride semiconductor layer.
8. A semiconductor device using a semiconductor wafer according to any one of claims 1 to 7, A first electrode provided on the second nitride semiconductor layer, The second electrode provided on the lower surface of the silicon carbide substrate, It is equipped with.
9. In the semiconductor device described in claim 8, The second nitride semiconductor layer and the first electrode are in Schottky contact to form a Schottky barrier diode.
10. In the semiconductor device described in claim 8, The semiconductor device further comprises a third nitride semiconductor layer and a fourth nitride semiconductor layer, which are inserted between the second nitride semiconductor layer and the first electrode. The third nitride semiconductor layer is provided on the second nitride semiconductor layer and is Al z Ga 1-z N (0 ≤ z ≤ 1) of the second conductivity type which is the opposite conductivity type to the first conductivity type. The fourth nitride semiconductor layer is provided on the third nitride semiconductor layer and is GaN of the second conductivity type. The semiconductor device is a pn junction diode.
11. In the semiconductor device according to claim 10, The Al composition within the third nitride semiconductor layer decreases as it approaches the interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer, starting from the lower surface of the third nitride semiconductor layer.

Description

Semiconductor wafers and semiconductor devices This disclosure relates to semiconductor wafers and semiconductor devices, and more particularly to technologies effective for use in semiconductor wafers and semiconductor devices having, for example, a silicon carbide substrate and an AlGaN layer. Japanese Patent Publication No. 2007-214515 (Patent Document 1) describes a technique for increasing the breakdown voltage of a nitride semiconductor device by using an AlGaN layer instead of a GaN layer as the voltage-holding layer. Specifically, an AlGaN layer is formed on an n-type SiC substrate via an AlGaN buffer layer. The Al composition of the AlGaN layer is greater than or equal to the Al composition of the AlGaN buffer layer. This allows for a higher breakdown voltage while suppressing crystal defects. Japanese Patent Publication No. 2007-59719 (Patent Document 2) describes a technique for sequentially forming an AlGaN layer with a high impurity concentration (Al composition > 0) and an AlBGaN layer with a low impurity concentration (Al composition ≥ 0, B composition ≥ 0) on a SiC substrate. Japanese Patent Publication No. 2000-40858 (Patent Document 3) describes an Al x Ga 1-x N layer (0 < x < 0.4 ) formed on a SiC substrate and having an n-type carrier concentration of 3 × 10¹⁸ (/cm³) to 1 × 10²⁰ ( / cm³ ). This is a cross-sectional view showing the configuration of a semiconductor wafer in Embodiment 1.This graph shows the dependence of the conduction band gap formed at the interface between the SiC substrate and the Al x Ga 1-x N layer on the Al composition x.This graph shows the relationship between the current density flowing in the first direction and the Al composition x.This graph shows the relationship between the current density flowing in the second direction and the Al composition x.This graph shows the relationship between the thickness of the contact layer and the impurity concentration.This is a cross-sectional view showing the configuration of a semiconductor device including a Schottky diode.This graph shows the relationship between the voltage between the upper and lower electrodes and the current density flowing through the Schottky diode.This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 2.This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 8.This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 9.This graph shows the relationship between the voltage between the upper and lower electrodes and the current density flowing through the Schottky diode.This is a cross-sectional view showing the configuration of a semiconductor device including a pn junction diode.This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 3.This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 13.This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 14. The following embodiments or examples refer to the accompanying drawings. Identical reference symbols (e.g., numbers and/or letters) in different drawings may indicate the same or similar elements. When used in this disclosure, terms indicating that one element (e.g., a layer, region, and/or substrate) is “on” or “over” another element may indicate that the element may be “directly on” or “indirectly above” another element, with or without the presence of an intervening element. Furthermore, when used in this disclosure, terms indicating that one element is “directly on” or “directly over” another element may indicate that there is no intervening element between them. In this disclosure, impurities can generally be referred to as having a conductivity type such that "first conductivity type" corresponds to n-type and "second conductivity type" corresponds to p-type. However, this definition may be reversed as appropriate. <Novel findings discovered by the inventors> The inventors have discovered, as a novel finding, that when manufacturing a vertical device using a semiconductor wafer in which an AlGaN layer is provided on a SiC substrate via an AlN buffer layer, the on-resistance becomes extremely high due to the AlN buffer layer (AlN layer). The following explains why the on-resistance becomes very high due to the AlN layer. First, let's explain electron affinity. Electron affinity refers to the difference between the vacuum energy level and the energy level at the conduction band edge. That is, if we denote electron affinity as "χ", the vacuum energy level as "Evac", and the energy level at the conduction band edge as "Ec", then χ = Evac - Ec. The electron affinity of SiC and AlN differs significantly. That is, the energy levels at the conduction band edge of SiC and AlN differ greatly. Therefore, a discontinuity at the conduction band edge o