WO-2026094488-A1 - SERIAL COMMUNICATION SYSTEM

Abstract

A serial communication system (1) comprises: n slave devices (21-28) having the same address; a master device (10); n switch ICs (41-48); and shift registers (31-32) capable of individually controlling ON/OFF of the n switch ICs (41-48). One clock signal line and one data signal line connected to the master device (10) respectively branch into n clock signal lines and n data signal lines, and are respectively connected to the n slave devices (21-28) via the n switch ICs (41-48). Said one clock signal line and one data signal line connected to the master device (10) further branch into and are connected to shift registers (31-32).

Inventors

• WATANABE KENICHI

Assignees

• パナソニックＩＰマネジメント株式会社

Dates

Publication Date

20260507

Application Date

20250926

Priority Date

20241029

Claims (6)

1. n (where n is an integer greater than or equal to 2) slave devices having the same address, A master device that communicates serially with the aforementioned n slave devices, n switch ICs for switching the n slave devices and the master device on and off, The system includes a shift register capable of individually controlling the on/off state of the n switch ICs, One clock signal line and one data signal line connected to the master device are each branched into n clock signal lines and n data signal lines, respectively, and connected to the n slave devices via the n switch ICs. The one clock signal line and the one data signal line connected to the master device are further branched and connected to the shift register. Serial communication system.
2. The master device and the shift register are further connected by a register clock signal line. The serial communication system according to claim 1.
3. The aforementioned shift registers include m (where m is an integer of 2 or more) shift registers, Each of the m shift registers controls the on/off state of some of the n switch ICs. The one clock signal line and the one register clock signal line connected to the master device each branch into m clock signal lines and m data signal lines, respectively, and are connected to the m shift registers. The master device and the m shift registers are daisy-chained together by a single branched data signal line. The serial communication system according to claim 2.
4. The master device uses the one clock signal line and the one data signal line to output a selection signal for selecting a specific switch IC from among the n switch ICs using a first serial communication method. The shift register controls the specific switch IC to the ON state according to the selection signal, After the specific switch IC is controlled to be ON, the master device communicates with a specific slave device via the specific switch IC using a second serial communication method, using the one clock signal line and the one data signal line. The serial communication system according to claim 1.
5. The master device is, Using the aforementioned one clock signal line and the aforementioned one data signal line, a selection signal is output in a first serial communication method to select a specific switch IC from among the n switch ICs. The register clock signal line is transitioned from inactive to active. The shift register latches the selection signal when the register clock signal line transitions from inactive to active, and controls the specific switch IC to the ON state according to the latched selection signal. The master device is, After the aforementioned specific switch IC is controlled to the ON state, the system communicates with a specific slave device via the specific switch IC using the one clock signal line and the one data signal line in a second serial communication method. When communication with the aforementioned specific slave device ends, the register clock signal line is transitioned from active to inactive. The shift register resets the latched selection signal and turns off the specific switch IC when the register clock signal line transitions from active to inactive. The serial communication system according to claim 2.
6. The first serial communication method is SPI (Serial Peripheral Interface), The second serial communication method described above is I2C (Inter-Integrated Circuit). The serial communication system according to claim 4 or 5.

Description

Serial communication system This disclosure relates to a serial communication system used for communication between one master device and multiple slave devices. In energy storage systems with multiple series-connected lithium-ion battery cells, it is necessary to measure and monitor the voltage of each lithium-ion battery cell. Since typical AFE (Analog Front End) ICs only support voltage measurement for a maximum of 16 cells, energy storage systems with more than 16 series-connected cells require the use of multiple AFE ICs. These multiple AFE ICs transmit the measured cell voltage, temperature, and current to the microcontroller via a serial communication interface. As a serial communication interface between an AFEIC and a microcontroller, I2C (Inter-Integrated Circuit) is commonly used, with the microcontroller as the master device and the AFEIC as the slave device. The I2C bus line uses two signal lines: the serial clock line (SCL) and the serial data line (SDA) (see, for example, Patent Document 1). Many inexpensive AFEICs have fixed I2C slave addresses. In systems using multiple AFEICs, such as energy storage systems, there is a need to use multiple AFEICs with the same slave address. When connecting multiple slave devices with the same address to a single master device, one option is to connect each of the slave devices via an I2C bus line (see Figure 1). However, this increases costs due to the need for multiple I2C bus lines. Furthermore, it is not possible to connect more slave devices than the number of I2C ports on the master device. Alternatively, an I2C switch IC could be installed between the master device and multiple slave devices, connecting the master device and the I2C switch IC with a single I2C bus line (see Figure 2). Even with this configuration, it's not possible to connect more slave devices than the number of I2C ports on the I2C switch IC. Daisy-chaining additional I2C switch ICs is also not easy. Furthermore, it's necessary to configure the I2C switch IC with a management slave address used by the master device, resulting in a cumbersome process. This figure shows an example configuration of a serial communication system according to Comparative Example 1.This figure shows an example configuration of a serial communication system according to Comparative Example 2.This figure shows an example configuration of a serial communication system according to Comparative Example 3.This figure shows an example configuration of a serial communication system according to an embodiment.This figure shows an example of a timing chart for a serial communication system according to an embodiment. Figure 1 shows an example configuration of serial communication system 1 according to Comparative Example 1. The serial communication system 1 according to Comparative Example 1 comprises a microcontroller 10, which is an I2C master device, and n (where n is an integer of 2 or more) I2C slave devices having the same address. Figure 1 shows an example where n=4, and the serial communication system 1 comprises a first slave device 21 to a fourth slave device 24. The microcontroller 10 and the first slave device 21 through the fourth slave device 24 are connected by I2C bus lines. Each I2C bus line consists of two signal lines: a serial clock line (SCL) and a serial data line (SDA). The microcontroller 10 has I2C ports with pins SCL0, SDA0, SCL1, SDA1, SCL2, SDA2, SCL3, and SDA3, and is connected to the first slave device 21 through the fourth slave device 24 via four I2C bus lines. In I2C, both the serial clock line (SCL) and the serial data line (SDA) use open-drain or open-collector output methods for the connected devices. Therefore, pull-up resistors must be connected to each serial clock line (SCL) and each serial data line (SDA). In the example shown in Figure 1, pull-up resistors R11-R14 are connected to each serial clock line (SCL), and pull-up resistors R21-R24 are connected to each serial data line (SDA). In this configuration, when not communicating, the serial clock line (SCL) and serial data line (SDA) are in a high-level state. As described above, in the configuration of Comparative Example 1, an I2C bus line must be installed for each slave device. Therefore, as the number of slave devices increases, the number of I2C bus lines also increases, leading to increased costs. Furthermore, since it is not possible to connect more slave devices than the number of I2C ports on the microcontroller 10, there is a limit to the number of slave devices that can be added. Figure 2 shows an example configuration of serial communication system 1 according to Comparative Example 2. Serial communication system 1 according to Comparative Example 2 includes a microcontroller 10 as an I2C master device, an I2C switch IC 60, and I2C first slave devices 21 to fourth slave devices 24 having the same address. The microcontroller 10 has SCL0 and SDA0 pins as I2C ports and is connected to the I2C switch IC 60 via