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WO-2026094655-A1 - ENCODING DEVICE AND DECODING DEVICE

WO2026094655A1WO 2026094655 A1WO2026094655 A1WO 2026094655A1WO-2026094655-A1

Abstract

The present disclosure pertains to an encoding device and a decoding device that enable suppression of image quality deterioration while maintaining throughput. In the present disclosure, a distributor divides a frame of an input image into pixel group units that serve as the smallest processing units for predictive encoding. A plurality of encoders predictively encode the pixels in the groups by sequentially switching for each of the divided groups. The present disclosure can be applied to, for example, an interface portion of an image sensor.

Inventors

  • ONO YOSHINORI
  • NAGUMO TAKEFUMI

Assignees

  • ソニーセミコンダクタソリューションズ株式会社

Dates

Publication Date
20260507
Application Date
20251017
Priority Date
20241101

Claims (18)

  1. A distributor that divides the input image frame into pixel groups that serve as the smallest processing unit for predictive coding, An encoding device comprising: a plurality of encoders that sequentially switch between each of the divided groups to predictively encode the pixels within the group.
  2. The encoding apparatus according to claim 1, further comprising a common line buffer that holds pixel data for each line processed by each of the encoders in a manner that can be commonly referenced by all of the encoders.
  3. The encoding apparatus according to claim 2, wherein the encoder predictively encodes the pixels in the group by referring only to the pixel data held in the common line buffer, without referring to the pixel data of the group that was immediately processed by another encoder.
  4. The encoding device according to claim 3, wherein the encoder further references the pixel data of the group that was processed two or more steps prior to perform predictive encoding of the pixels in the group.
  5. The encoding apparatus according to claim 1, further comprising an individual line buffer in which each of the encoders individually holds pixel data for each line processed by each of the encoders, so that each encoder can individually refer to it.
  6. The encoding device according to claim 5, wherein the encoder predictively encodes the pixels in the group by referring only to the pixel data held in the individual line buffer, without referring to the pixel data of the group that was processed in the previous step.
  7. The encoding device according to claim 6, wherein the encoder further references the pixel data of the group that was processed two or more steps prior to perform predictive encoding of the pixels within the group.
  8. The encoding apparatus according to claim 1, further comprising a color history manager that maintains the color history of the pixels processed by each of the encoders in a manner that can be commonly referenced by all of the encoders.
  9. A distributor that divides the encoded stream into pixel groups that form the smallest processing unit for predictive coding, A decoding device comprising: a plurality of decoders that sequentially switch between each of the divided groups to predict and decode the pixels within the group.
  10. The decoding apparatus according to claim 9, further comprising a common line buffer that holds pixel data for each line processed by each of the decoders in a manner that can be commonly referenced by all of the decoders.
  11. The decoding apparatus according to claim 10, wherein the decoder predicts and decodes the pixels in the group by referring only to the pixel data held in the common line buffer, without referring to the pixel data of the group that was processed immediately before by another decoder.
  12. The decoding apparatus according to claim 11, wherein the decoder further references the pixel data of the group that was processed two or more steps prior to predict and decode the pixels in the group.
  13. The decoding apparatus according to claim 9, further comprising an individual line buffer that holds pixel data for each line processed by each of the decoders in a manner that each decoder can individually access.
  14. The decoding apparatus according to claim 13, wherein the decoder predicts and decodes the pixels in the group by referring only to the pixel data held in the individual line buffer, without referring to the pixel data of the group that was processed in the previous step.
  15. The decoding apparatus according to claim 14, wherein the decoder further refers to the pixel data of the group that was processed two or more steps prior to predict and decode the pixels within the group.
  16. The decoding apparatus according to claim 9, further comprising a color history manager that maintains the color history of the pixels processed by each of the decoders in a manner that can be commonly referenced by all of the decoders.
  17. A distributor that divides the input image frame into M regions which will be the processing units for predictive coding, An encoding device comprising N encoders that predictively encode M/N (N << M) pixels within the region that are not spatially adjacent.
  18. A distributor that divides the encoded stream into M regions which will be the processing units for predictive coding, A decoding device comprising N decoders that predict and decode M/N pixels (N << M) within the region that are not spatially adjacent.

Description

Encoding device and decoding device This disclosure relates to encoding and decoding devices, and more particularly to encoding and decoding devices that can suppress image quality degradation while maintaining throughput. In recent years, with the increase in image resolution, frame rates, and dynamic range, the amount of data has also increased. In particular, the bandwidth requirements for the interface in each system have become more stringent, and there are also challenges related to power consumption. In response to this, methods to reduce bandwidth through data compression technology are employed. For example, VESA has established a standard called DSC for image data compression for displays. DSC is a lossy compression transmission technology that reduces transmission bandwidth by applying irreversible compression to image data. This compression transmission technology is required to be at a level where the degradation is imperceptible to the human eye. In DSC (Digital Screen Display), "slice division" is performed to divide the screen vertically and horizontally in order to achieve a predetermined throughput in hardware implementation. However, especially when slicing vertically, gaps in the compression mode can occur at the boundaries between slices, sometimes resulting in perceived degradation near those boundaries. In response to this, Patent Document 1 discloses a technique to reduce visual artifacts between slices by adjusting the quantization parameters of blocks adjacent to the slice boundaries. This figure shows an example of a vertical 4-part slice division.This diagram explains the rate control function.This diagram illustrates the pixel positions referenced in predictive coding.This diagram illustrates slice division using the smallest processing unit.This is a diagram illustrating the pixel reference in the technology related to this disclosure.This figure shows an example configuration of an image processing system according to the first embodiment of this disclosure.This is a block diagram showing an example configuration of an encoding device.This diagram illustrates the processing order of predictive coding.This is a block diagram showing an example of the encoding core configuration.This figure shows an example of pixel referencing in the first embodiment.This is a block diagram showing an example configuration of a predictor, quantizer, and reconstructor.This figure shows another example of pixel referencing in the first embodiment.This is a block diagram showing other examples of predictor, quantizer, and reconstructor configurations.This figure shows yet another example of pixel referencing in the first embodiment.This diagram illustrates a specific example of a prediction method.This diagram illustrates a specific example of a prediction method.This diagram illustrates a specific example of a prediction method.This diagram illustrates a specific example of a prediction method.This diagram illustrates a specific example of a prediction method.This is a block diagram showing an example configuration of a decoding device.This is a block diagram showing an example of a decoder core configuration.This is a block diagram showing an example configuration of a predictor, quantizer, and reconstructor.This figure shows an example configuration of an image processing system according to a second embodiment of the present disclosure.This is a block diagram showing an example configuration of an encoding device.This is a block diagram showing an example of the encoding core configuration.This figure shows an example of pixel referencing in the second embodiment.This figure shows another example of pixel referencing in the second embodiment.This figure shows yet another example of pixel referencing in the second embodiment.This is a block diagram showing an example configuration of a decoding device.This is a block diagram showing an example of a decoder core configuration.This figure shows a modified image processing system.This diagram illustrates slicing at arbitrary processing units.This is a block diagram showing variations of coding devices.This is a block diagram showing a modified version of a decoding device.This figure shows an example of a pixel block, which is the unit of processing. The following describes the forms for implementing this disclosure (hereinafter referred to as "embodiments"). The description will be given in the following order. 1. Background 2. Conventional Technology and its Challenges 3. Overview of the Technology Related to This Disclosure 4. First Embodiment (Configuration Sharing a Line Buffer) 5. Second Embodiment (Configuration without shared line buffer) 6. Modified Examples 7. Effects of the Disclosure <1. Background＞ In recent years, with the increase in image resolution, frame rates, and dynamic range, the amount of data has also increased. In particular, the bandwidth requirements for each system have become stricter in the interface section, and ther