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WO-2026094733-A1 - SEMICONDUCTOR DEVICE

WO2026094733A1WO 2026094733 A1WO2026094733 A1WO 2026094733A1WO-2026094733-A1

Abstract

This semiconductor device includes: an SiC chip that has a main surface having set therein an active region in which an element structure is formed and an outer peripheral region which is located around the active region; a first impurity region that exhibits a first conductivity type and that is formed in a surface layer portion of the main surface; a second impurity region that exhibits a second conductivity type, that has a first concentration, and that is formed in a surface layer portion of the first impurity region at the outer peripheral region; and a separation impurity region that separates the first impurity region from the second impurity region at the outer peripheral region and that has a second concentration lower than the first concentration.

Inventors

  • TANIMOTO, Yuta
  • NAKANO, YUKI
  • MORI, Seigo

Assignees

  • ローム株式会社

Dates

Publication Date
20260507
Application Date
20251022
Priority Date
20241028

Claims (20)

  1. A SiC chip having a main surface in which an active region on which an element structure is formed and an outer peripheral region surrounding the active region are defined, A first impurity region of the first conductivity type formed on the surface layer of the main surface, In the outer peripheral region, a second impurity region of a second conductivity type having a first concentration is formed on the surface of the first impurity region, A semiconductor device comprising a first impurity region and a second impurity region separated in the outer peripheral region, and including a separated impurity region having a second concentration lower than the first concentration.
  2. The main surface is a surface inclined with an off angle θ in a first direction which is a predetermined off direction with respect to the (0001) surface, The semiconductor device according to claim 1, wherein the separated impurity region is formed at least along a second direction that intersects the first direction in a plan view.
  3. The first direction is the [11-20] direction, The semiconductor device according to claim 2, wherein the second direction is the [1-100] direction.
  4. The semiconductor device according to claim 2 or 3, wherein the separated impurity region is formed along the first and second directions, extending over the entire circumference of the outer edge of the SiC chip.
  5. The SiC chip is formed in a rectangular shape in plan view, having a pair of first sides along the first direction and a pair of second sides along the second direction. The separated impurity region comprises a pair of first separation regions along the pair of first side surfaces and a pair of second separation regions along the pair of second side surfaces. The semiconductor device according to any one of claims 2 to 4, wherein the width of the second separation region is wider than the width of the first separation region.
  6. The SiC chip is formed in a rectangular shape in plan view, having a pair of first sides along the first direction and a pair of second sides along the second direction. The semiconductor device according to any one of claims 2 to 4, wherein the separated impurity region is formed along the pair of first sides and not along the pair of second sides.
  7. The SiC chip has a pair of first surfaces aligned along the [11-20] direction and a pair of second surfaces aligned along the [1-100] direction. The separated impurity region comprises a pair of first separation regions along the pair of first side surfaces and a pair of second separation regions along the pair of second side surfaces. The semiconductor device according to any one of claims 1 to 4, wherein the width of the second separation region is wider than the width of the first separation region.
  8. The SiC chip has a pair of first surfaces aligned along the [11-20] direction and a pair of second surfaces aligned along the [1-100] direction. The semiconductor device according to any one of claims 1 to 4, wherein the separated impurity region is formed along the pair of first sides and not along the pair of second sides.
  9. A semiconductor device according to any one of claims 1 to 8, further comprising a main surface insulating film covering at least a portion of the main surface.
  10. The semiconductor device according to claim 9, wherein the main surface insulating film covers the entire separated impurity region.
  11. The main surface insulating film has an end portion located away from the side surface of the SiC chip towards the active region. The semiconductor device according to claim 9, wherein the second impurity region is exposed from the main surface insulating film in a plan view.
  12. The semiconductor device according to claim 9, wherein the main surface insulating film covers the main surface from the active region to the side surface of the SiC chip.
  13. The element structure comprises a main surface electrode electrically connected to the above element structure, It includes an interlayer insulating film disposed between the main surface insulating film and the SiC chip, which supports the main surface electrode, The semiconductor device according to any one of claims 9 to 12, wherein the interlayer insulating film covers the separated impurity region and the second impurity region.
  14. The semiconductor device according to any one of claims 9 to 13, wherein the main surface insulating film comprises at least one of an oxide film, a nitride film, and a polyimide film.
  15. The semiconductor device according to claim 14, wherein the main surface insulating film comprises a single layer film selected from an oxide film, a nitride film, and a polyimide film.
  16. The semiconductor device according to any one of claims 9 to 15, wherein the SiC chip includes a recess formed on the main surface in the outer peripheral region, having a bottom surface in which at least the second impurity region is exposed.
  17. The semiconductor device according to claim 16, wherein the recess has a tapered side surface that is inclined with respect to the main surface.
  18. The semiconductor device according to claim 16 or 17, wherein the recess includes a lateral open recess having an open end on the side of the SiC chip and a side on the opposite side.
  19. The SiC chip includes a mesa portion formed inside the recess, The semiconductor device according to any one of claims 16 to 18, wherein the main surface insulating film covers the mesa portion and the recess.
  20. The semiconductor device according to any one of claims 1 to 19, wherein the separated impurity region is an impurity region of a first conductivity type or a second conductivity type.

Description

Semiconductor equipment Related applications This application corresponds to Japanese Patent Application No. 2024-188782, filed with the Japan Patent Office on October 28, 2024, and the full disclosure of that application is incorporated herein by reference. This disclosure relates to semiconductor devices. Patent Document 1 discloses a semiconductor device comprising an n-type SiC epitaxial layer, a source metal on the SiC epitaxial layer, a passivation film made of an organic insulator arranged to cover the source metal, an end insulating film extending from a dicing region set at the end of the SiC epitaxial layer toward the source metal and positioned below the passivation film, and a metal-under insulating film positioned below the source metal, wherein the distance from the end of the dicing region in the end insulating film toward the passivation film is longer than the distance extending from the end of the passivation film toward the source metal in the end insulating film. Figure 1 is a plan view showing a semiconductor device according to one embodiment of the present disclosure.Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1.Figure 3 is a perspective view showing an example of a chip layout.Figure 4A is an enlarged plan view of the main part of the SiC chip.Figure 4B is a cross-sectional view along the IVB-IVB line shown in Figure 4A.Figure 5 is a plan view showing the main part of the active region.Figure 6 is a perspective view showing the main part of the active region.Figure 7 is a perspective view showing the main part of the active region.Figure 8 is a cross-sectional view showing the main part of the active region.Figure 9 is a perspective view showing a modified example of the device structure.Figure 10 is a perspective view showing a modified example of the device structure.Figure 11 is a plan view showing an example of the layout of the outer perimeter structure.Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 11.Figure 13 is a cross-sectional view along the line XIII-XIII shown in Figure 11.Figure 14 is a plan view showing an example of the layout of the outer perimeter structure.Figure 15 is a plan view showing an example of the layout of the outer perimeter structure.Figure 16 is a cross-sectional view along the line XVI-XVI shown in Figure 15.Figure 17 is a plan view showing an example of the layout of the outer perimeter structure.Figure 18 is a cross-sectional view showing a modified example of the outer perimeter structure.Figure 19 is a cross-sectional view showing a modified example of the outer periphery structure.Figure 20 is a cross-sectional view showing a modified example of the outer periphery structure.Figure 21 is a cross-sectional view showing a modified example of the outer periphery structure.Figure 22 is a cross-sectional view showing a modified example of the outer perimeter structure.Figure 23 is a cross-sectional view showing a modified example of the outer perimeter structure.Figure 24 is a cross-sectional view showing a modified example of the outer perimeter structure.Figure 25 is a cross-sectional view showing a modified example of the outer perimeter structure.Figure 26 is a cross-sectional view showing a modified example of the outer perimeter structure. [Detailed explanation] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments will be described in detail below with reference to the attached drawings. The attached drawings are schematic diagrams and not strictly accurate; the scale, proportions, angles, etc., do not necessarily correspond. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies. In this specification, where the term "substantially" is used, it includes not only numerical values (forms) equal to the comparative numerical value (form), but also numerical errors (form errors) within a range of ±10% from the comparative numerical value (form). In the following descriptions, terms such as "first," "second," and "third" are used; these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure. In the following explanation, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is the conductivity type resulting from trivalent elements, and "n-type" is the conductivity type resulting from pentavalent elements. Unless otherwise speci