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WO-2026094782-A1 - SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

WO2026094782A1WO 2026094782 A1WO2026094782 A1WO 2026094782A1WO-2026094782-A1

Abstract

This semiconductor device comprises: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface and made of an epitaxial layer; an active region provided in a portion inside of the main surface; an outer peripheral region provided in a peripheral portion of the main surface and surrounding the periphery of the active region; a device structure formed in the active region; a first field region of a second conductivity type formed in a surface layer portion of the semiconductor region in the outer peripheral region at an interval from the main surface in the depth direction of the chip; and a surface region of the first conductivity type formed in the surface layer portion of the semiconductor region in the outer peripheral region and sandwiching the first field region between the surface region and the semiconductor region in the depth direction of the chip, the surface region containing impurities of the second conductivity type.

Inventors

  • NAKANO, YUKI

Assignees

  • ローム株式会社

Dates

Publication Date
20260507
Application Date
20251023
Priority Date
20241031

Claims (20)

  1. A chip having a main surface, A first conductivity type semiconductor region, formed on the surface layer of the main surface and consisting of an epitaxial layer, An active region provided in the inner part of the main surface, A peripheral region is provided on the periphery of the main surface, and surrounds the periphery of the active region, A device structure formed within the active region, In the outer peripheral region, a first field region of a second conductivity type is formed on the surface layer of the semiconductor region at a distance from the main surface in the depth direction of the chip, A semiconductor device comprising a surface region formed in the outer peripheral region on the surface layer of the semiconductor region, which is a surface region of a first conductivity type that sandwiches the first field region in the depth direction of the chip and contains a second conductivity type impurity, between itself and the semiconductor region.
  2. The aforementioned chip has a concentration gradient of a second conductive impurity, The semiconductor device according to claim 1, wherein the concentration gradient increases in at least a portion of the surface region as it moves from the main surface side toward the first field region side.
  3. The semiconductor device according to claim 2, wherein the concentration gradient includes a peak portion in the first field region.
  4. The semiconductor device according to any one of claims 1 to 3, wherein the concentration of the first conductivity type impurity in the surface region is higher than the concentration of the first conductivity type impurity in the semiconductor region.
  5. The semiconductor region includes a first epitaxial layer and a second epitaxial layer laminated on the first epitaxial layer, the second epitaxial layer having a higher concentration of first conductivity type impurities than the first epitaxial layer. The first field region is formed in the first epitaxial layer, The semiconductor device according to any one of claims 1 to 4, wherein the surface region is formed in the second epitaxial layer.
  6. The semiconductor device according to claim 5, wherein the concentration ratio of the first conductivity type impurity concentration in the second epitaxial layer to the concentration of the first conductivity type impurity concentration in the first epitaxial layer is greater than 1 and less than or equal to 10.
  7. The outer peripheral region further includes a second field region of a second conductivity type formed in the second epitaxial layer and facing the first field region with a portion of the second epitaxial layer in between, The aforementioned surface region A first surface region formed in the second epitaxial layer and sandwiched in the depth direction of the chip by the first field region and the second field region, The semiconductor device according to claim 5 or 6, comprising a second surface region formed in the second epitaxial layer and in the region between the second field region and the main surface.
  8. The semiconductor device according to claim 7, wherein the concentration of the second conductivity type impurity in the second field region is higher than the concentration of the second conductivity type impurity in the first field region.
  9. The aforementioned chip has a concentration gradient of a second conductive impurity, The semiconductor device according to claim 7 or 8, wherein the concentration gradient increases in the second surface region as it moves from the main surface side towards the second field region side.
  10. The semiconductor device according to claim 9, wherein the concentration gradient includes a first peak portion in the second field region.
  11. The semiconductor device according to claim 10, wherein the concentration gradient includes a second peak portion having a peak value smaller than the peak value in the first peak portion within the first field region.
  12. The semiconductor device according to any one of claims 7 to 11, wherein the second field region has a second thickness smaller than the first thickness in the depth direction of the chip in the first field region.
  13. The first field region is formed with intervals between them and includes a plurality of annular first field regions surrounding the active region. The semiconductor device according to any one of claims 1 to 12, wherein the surface regions are formed at intervals from one another and include a plurality of annular surface regions surrounding the active region.
  14. The chip further has sides, The semiconductor region is exposed on the side surface, The semiconductor device according to any one of claims 1 to 13, wherein the outermost of the plurality of first field regions is formed at a distance from the side surface.
  15. The semiconductor device according to any one of claims 1 to 14, wherein the first field region is in an electrically floating state.
  16. The semiconductor device according to any one of claims 1 to 15, wherein the chip includes a SiC chip.
  17. A step of preparing a wafer in which a first epitaxial layer of the first conductivity type is formed on a semiconductor substrate of the first conductivity type, a second epitaxial layer of the first conductivity type having a higher concentration of first conductivity type impurities than the first epitaxial layer is formed on the first epitaxial layer, and the wafer main surface is formed on the second epitaxial layer, A method for manufacturing a semiconductor device, comprising: a first ion implantation step of implanting ions of a second conductivity type from the main surface of the wafer toward the first epitaxial layer such that the concentration of second conductivity type impurities in a portion of the first epitaxial layer exceeds the concentration of first conductivity type impurities, thereby forming a first field region of the second conductivity type in the first epitaxial layer.
  18. A method for manufacturing a semiconductor device according to claim 17, further comprising a second ion implantation step of implanting ions of a second conductivity type from the main surface of the wafer toward the second epitaxial layer such that the concentration of the second conductivity type impurity in a portion of the second epitaxial layer exceeds the concentration of the first conductivity type impurity, thereby forming a second field region of the second conductivity type in the second epitaxial layer.
  19. The method for manufacturing a semiconductor device according to claim 18, wherein the second ion implantation step is performed after the first ion implantation step.
  20. The first ion implantation step includes implanting ions of a second conductivity type from the main surface of the wafer toward the first epitaxial layer via a mask, The method for manufacturing a semiconductor device according to claim 18 or 19, wherein the second ion implantation step includes implanting ions of a second conductivity type from the main surface of the wafer toward the second epitaxial layer via the mask.

Description

Semiconductor device and method for manufacturing a semiconductor device Related applications This application corresponds to Japanese Patent Application No. 2024-192346, filed with the Japan Patent Office on October 31, 2024, and the full disclosure of that application is incorporated herein by reference. This disclosure relates to semiconductor devices and methods for manufacturing the same. In the semiconductor device disclosed in Patent Document 1 (US8294235B2), a p- region is embedded in the surface layer of an n-type epitaxial layer. The p- region is sandwiched between a region on the surface side of the p- region (n-type epitaxial layer) and a region on the back side of the p- region (n-type epitaxial layer). That is, an n-p-n sandwich structure is formed in the surface layer of the n-type epitaxial layer. The p- region is exposed on the side surface of the chip. Figure 1 is a plan view showing a semiconductor device according to the first embodiment of this disclosure.Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1.Figure 3 is a plan view showing an example of a chip layout.Figure 4 is a perspective view showing an example of a chip layout.Figure 5 is an enlarged plan view showing a key part of the first main surface shown in Figure 3.Figure 6 is an enlarged plan view showing a key part of the first main surface shown in Figure 3.Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 5.Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 5.Figure 9 is a cross-sectional view showing the cross-sectional structure of the outer region along the IX-IX line shown in Figure 1.Figure 10 is an enlarged cross-sectional view of one region shown in Figure 9.Figure 11 is a plan view showing an example of a chip layout.Figure 12 is a graph showing an example of the concentration gradient of p-type impurities in the region along the XII-XII line shown in Figure 10 (first example).Figure 13 is a graph showing an example of the concentration gradient of n-type impurities in the region along the XII-XII line shown in Figure 10.Figure 14 is a schematic diagram showing a wafer used in the manufacture of the semiconductor device.Figure 15A is a cross-sectional view showing the method for manufacturing the semiconductor device.Figure 15B is a cross-sectional view showing a process after Figure 15A.Figure 15C is a cross-sectional view showing a process after Figure 15B.Figure 15D is a cross-sectional view showing a process after Figure 15C.Figure 15E is a cross-sectional view showing a process after Figure 15D.Figure 15F is a cross-sectional view showing a process after Figure 15E.Figure 15G is a cross-sectional view showing a process after Figure 15F.Figure 16A is a graph showing a second example of the concentration gradient of p-type impurities in the chip, and corresponds to Figure 12.Figure 16B is a graph showing a third example of the concentration gradient of p-type impurities in the chip, and corresponds to Figure 12.Figure 16C is a graph showing a fourth example of the concentration gradient of p-type impurities in the chip, and corresponds to Figure 12.Figure 17 is a cross-sectional view showing the field region and surface region related to the first modified example.Figure 18 is a cross-sectional view showing the cross-sectional structure of the outer peripheral region according to the second embodiment of the present disclosure, and corresponds to Figure 10.Figure 19 is a graph showing an example of the concentration gradient of p-type impurities in the region along the XIX-XIX line shown in Figure 18 (Example of the fifth form).Figure 20A is a cross-sectional view showing the method for manufacturing the semiconductor device.Figure 20B is a cross-sectional view showing a process that follows Figure 20A.Figure 20C is a cross-sectional view showing a process after Figure 20B.Figure 20D is a cross-sectional view showing a process after Figure 20C.Figure 20E is a cross-sectional view showing a process that follows Figure 20D.Figure 21A is a graph showing a sixth example of the concentration gradient of p-type impurities in the chip, and corresponds to Figure 19.Figure 21B is a graph showing a seventh example of the concentration gradient of p-type impurities in the chip, and corresponds to Figure 19.Figure 22 is a cross-sectional view showing the field region and surface region related to the second modified example.Figure 23 is a cross-sectional view showing the main part of a semiconductor device according to the third embodiment of this disclosure.Figure 24 is a cross-sectional view showing the main part of the semiconductor device.Figure 25 is a cross-sectional view showing the main part of a semiconductor device according to the fourth embodiment of this disclosure. [Detailed explanation] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The attached drawings are all s