WO-2026095829-A1 - CONFIGURABLE ASSOCIATIVE CONVERSION MEMORY AND OPERATING METHOD THEREOF

WO2026095829A1WO 2026095829 A1WO2026095829 A1WO 2026095829A1WO-2026095829-A1

Abstract

The invention relates to computing, and more particularly to (sub)processors in an associative, synchronous, FIFO register, conversion memory. The technical results consist in an increase in reliable diagnostic capability in SIMD mode, and conflict-free multi-stream processing of instructions and data in MIMD mode. A configurable associative, FIFO register, conversion memory is configured in the form of a computing surface comprised of operating bits and permits the formation of a part or the whole of a connected orientable computing surface of genus 0 or more. The claimed method comprises (micro)programmably configuring or reconfiguring a computing surface by a part or the whole of a connected orientable surface of genus 0 or more, carrying out testing in SIMD mode, excluding operating bits that fail information transfer and/or conversion process tests, (micro)programmably changing the genus of the connected orientable computing surface, and using said surface in information processes.

Inventors

ALAKOZ, Gennadii
BYDANOV, Nikolai
ZHELEZNIAK, Vladimir
PLIASKOTA, Sergei
POPOV, Aleksei
SERIKOV, Aleksandr
TORITSYN, Igor
SHVED, Vladimir
SHIRINKIN, Viktor

Dates

Publication Date: 20260507
Application Date: 20250503
Priority Date: 20241103

Claims (10)

1. A configurable converting 11111 U-register associative memory in the form of a computing surface of operational bits, synchronously operating and united by a single U-register channel for input and storage of configuring bit instructions, switched with a memory configuration control controller and a programmer via a system bus, intended for computer applications of (multi)stream information processing and included in (sub)processor paths in the form of pre-, co- and post-processors interacting with each other via a (micro)software-reconfigurable loop-bus, ensuring the formation of computing: parts of a connected orientable surface of genus 0 or a connected orientable surface of genus 0 and higher.
2. Memory according to paragraph 1, characterized in that the operational bits combine the computing functionalities of storage, transfer and conversion in terms of hardware and time, and the content of the stored, transferred and converted information is used for the dynamic (re)configuration of the structure of the computing surface.
3. Memory according to claim 1, characterized in that in the computing surface the operational bits are connected by bidirectional galvanic connections with the nearest orthogonal neighbors.
4. Memory according to claim 1, characterized in that the computing surface includes input and output interfaces for physical coupling with external devices, including an interface for bidirectional information exchange with a memory configuration controller, flash memory of firmware for application functionality and diagnostics, storing input and output signatures of diagnostic data, with the ability to be configured by circuitry and (micro)software in a time-sharing mode with information processing with virtualization of its address space by segmentation at the stage of memory configuration of arbitrary volumes and at the stage of normal operation to be reconfigured in real time (micro)software and/or the contents of converted data streams.
5. The memory according to claim 1, characterized in that the operational bits include a converting complementary static D-flip-flop, which is part of a distributed over the VLSI equidistant in time delay PPPO-register structure, the ^-outputs of which set and fix for a certain period of time the Config/Processing memory segments operating mode synchronously and in-phase across all operational bits of the segment, a configuration register of complementary static converting D-flip-flops, which is part of the input and storage channel of user-defined configurations of memory segments, a distributed decoder converting the contents of the register into control signals for (micro)command-controlled volatile electronic keys, an input and output switching field of volatile electronic keys of addressless data exchange with the nearest orthogonal operational bits, a two-layer operational device of clusters of converting complementary static D-flip-flops, the configuration of connections between which is specified by the switching field energy-dependent electronic keys that provide addressless data exchange.
6. The memory according to claim 5, characterized in that a non-volatile switch is included in the complementary static D-triggers, which ensures the distribution of complementary signals (in, -, Ui) along two transmission channels formed by two D-triggers of the TT type and a non-volatile switch, which ensure the distribution of signals between four D-triggers of the T type and an output non-volatile switch, which ensures the distribution of complementary signals to the outputs (u + 1, -, m 1+ 1) and Qi, from which the complementary signals to the outputs (u (+ 1, -, m 1+ 1) are used to form 1111110- registers of arbitrary bit capacity, and Qi is used to fix the state of each bit of the configuration register, which determines the state of the volatile keys in the corresponding components of the operational bits.
7. A method of operating a configurable transforming PPPO-register associative memory, in which the computing surface is (micro)programmatically configured or reconfigured as a part of a connected orientable surface of genus 0 or a connected orientable surface of genus 0 and higher, tested in the OKMD mode, operational bits that have not passed the tests are excluded from the processes of transmitting and/or converting information, the type of connected orientable is (micro)programmatically changed computing surface and are used in the processes of storing, transmitting and/or converting information.
8. The method according to claim 7, characterized in that the type of the connected orientable computational surface is changed by increasing.
9. The method according to claim 7, characterized in that the type of the connected orientable computational surface is changed by decreasing.
10. The method according to claim 7, characterized in that the type of connected orientable computing surface is (micro)programmatically changed by puncturing areas of operational bits that have not passed the tests.

Description

Configurable transformative associative memory and its operating method Field of technology The inventions relate to computing technology, in particular to computing complexes, fine-grained structural-functional reconfigurable (sub)processors in converting, synchronous, PPPO-register, associative memory. The abbreviation PPPO stands for “first come, first served”, similar to “first in, first out” (FIFO). State of the art Similar in technical essence is the “Module of a homogeneous computing structure” according to the USSR Author’s Certificate for Invention No. 1359782, which was published on 15.12.1987, according to IPC G06F 15/00, including an arithmetic logic unit, a command register, delay elements, input switching units, output switching units, a transit control unit, and a transit expansion unit. Similar in technical essence is a device implemented, according to the information from the source “Software synthesis of arrays of processor elements”, US patent for invention No. 6507947, which was published on 01/14/2003, according to IPC G06F 9/45, including a generated array of processors with arithmetic logic units, command registers, delay elements, input switching units, output switching units, and a transit control unit. Similar in technical essence is the “Array of reconfigurable processors with a zero-buffer pipeline” according to the Chinese patent application No. 112506853, which was published on March 16, 2021, under IPC G06F 15/78, including reconfigurable processor units, local registers, global registers, and buses. The disadvantages of the above-mentioned devices include insufficient reliable diagnostic suitability and low conflict-free multi-threaded processing of instructions and data. The closest in technical essence is the “Cell of a homogeneous computing environment” according to the USSR Author’s Certificate for Invention No. 691846, which was published on October 15, 1979, according to IPC G06F 7/00, including an arithmetic logic element, a command register, delay elements, input switches, output switches, a transit circuit, and a transit expansion unit. The disadvantages of the above-mentioned device include insufficiently high reliable diagnostic suitability and low conflict-free multi-threaded processing of instructions and data. Disclosure of inventions The increased packaging density of electronic components is currently achieved by reducing the component size—using VLSI manufacturing technologies with components smaller than 10 nm. This allows for increased VLSI performance and reduced power consumption. However, reducing component size can lead to malfunctions in some VLSI components. To improve VLSI reliability, it is important to perform component diagnostics during operation, eliminating malfunctioning VLSI components from use. The objectives of the invention are to improve reliable diagnostics and create conflict-free multi-threaded processing of instructions and data. The technical results of the inventions are an increase in reliable diagnostic suitability in the OKMD mode and the creation of conflict-free multi-threaded processing of instructions (commands) and data in the MKMD mode. 1 SUBSTITUTE SHEET (RULE 26) The abbreviation "Single Instruction Stream/Multiple Data Stream" (SIMD) stands for "Single Instruction Stream/Multiple Data Stream," analogous to M. Flynn's "Single Instruction Stream/Multiple Data Stream." The abbreviation "Multiple Instruction Stream/Multiple Data Stream" (MIMD) stands for "Multiple Instruction Stream/Multiple Data Stream," analogous to M. Flynn's "Multiple Instruction Stream/Multiple Data Stream." The technical results are achieved by the fact that the configurable converting PPPO-register associative memory is implemented in the form of a computing surface of operational bits (OB), synchronously operating and united by a single PPPO-register channel for input and storage of configuring bit instructions, switched with the memory configuration control controller and the programmer via a system bus, intended for computer applications of (multi)stream information processing and included in (sub)processor paths in the form of pre-, co- and postprocessors interacting with each other via a (micro)software-reconfigurable loop-bus, ensuring the formation of computing: parts of a connected orientable surface of genus 0 or a connected orientable surface of genus 0 and higher. Technical results are also achieved by the fact that in the configurable converting PPPO-register associative memory, operational bits can be combined in hardware and time with the computing functionalities of storage, transfer and conversion, and the content of the stored, transferred and converted information can be used for the dynamic (re)configuration of the structure of the computing surface. Technical results are also achieved by the fact that in the computing surface, operational bits can be connected by bidirectional galvanic connections with their nearest orthogonal nei