WO-2026095971-A1 - PROGRAM REFRESH FOR NON-VOLATILE MEMORY CELLS

Abstract

A programming method for a semiconductor device that includes programming a first memory cell to a first program state that is associated with a first program verify voltage and a first reference voltage such that the first memory cell has a first threshold voltage that meets or exceeds the first program verify voltage. The first program verify voltage is greater than the first reference voltage. A first read operation is performed which determines the first threshold voltage of the first memory cell has drifted down to between the first program verify voltage and the first reference voltage. In response to this determination, the first memory cell is programmed to increase the first threshold voltage of the first memory cell to meet or exceed the first program verify voltage.

Inventors

• SURICO, STEFANO
• BARTOLI, SIMONE
• SIVERO, STEFANO
• MOIOLI, Guiseppe
• LIU, XIAN
• LE, THAI
• VO, An

Assignees

• SILICON STORAGE TECHNOLOGY, INC.

Dates

Publication Date

20260507

Application Date

20250117

Priority Date

20250113

Claims (20)

1. 1. A programming method for a semiconductor device, comprising: programming a first memory cell to a first program state that is associated with a first program verify voltage and a first reference voltage such that the first memory cell has a first threshold voltage that meets or exceeds the first program verify voltage, wherein the first program verify voltage is greater than the first reference voltage; determining in a first read operation that the first threshold voltage of the first memory cell has drifted down to between the first program verify voltage and the first reference voltage; and in response to the determining in the first read operation, programming the first memory cell to increase the first threshold voltage of the first memory cell to meet or exceed the first program verify voltage.
2. 2. The method of claim 1, comprising: determining the first memory cell is programmed to the first program state by performing a second read operation to determine the first threshold voltage of the first memory cell meets or exceeds the first reference voltage.
3. 3. The method of claim 1, wherein the determining in the first read operation comprises determining that the first threshold voltage of the first memory cell has drifted down to between a first refresh verify voltage and the first reference voltage, wherein the first refresh verify voltage is less than the first program verify voltage.
4. 4. The method of claim 1, comprising: programming a second memory cell to a second program state that is associated with a second program verify voltage and a second reference voltage such that the second memory cell has a second threshold voltage that meets or exceeds the second program verify voltage and that is less than the first reference voltage, wherein the second program verify voltage is greater than the second reference voltage, and wherein the second program verify voltage and the second reference voltage are less than the first reference voltage; 21 1616418352.1 Atty Dckt No.: 351918-981032 PATENT determining in a second read operation that the second threshold voltage of the second memory cell has drifted down to between the second program verify voltage and the second reference voltage; and in response to the determining in the second read operation, programming the second memory cell to increase the second threshold voltage of the second memory cell to meet or exceed the second program verify voltage.
5. 5. The method of claim 4, wherein the programming of the first memory cell in response to the determining in the first read operation is performed before the programming of the second memory cell in response to the determining in the second read operation.
6. 6. The method of claim 4, comprising: determining the second memory cell is programmed to the second program state by performing a third read operation to determine the second threshold voltage of the second memory cell meets or exceeds the second reference voltage and is lower than the first reference voltage.
7. 7. The method of claim 4, wherein the determining in the second read operation comprises determining that the second threshold voltage of the second memory cell has drifted down to between a second refresh verify voltage and the second reference voltage, wherein the second refresh verify voltage is less than the second program verify voltage.
8. 8. The method of claim 4, wherein the first and second read operations are performed before the programming of the first memory cell in response to the determining in the first read operation and the programming of the second memory cell in response to the determining in the second read operation.
9. 9. The method of claim 1, comprising: programming a second memory cell to a second program state that is associated with a second program verify voltage and a second reference voltage such that the second memory cell has a second threshold voltage that meets or exceeds the second program verify voltage, 22 1616418352.1 Atty Dckt No.: 351918-981032 PATENT wherein the second program verify voltage is greater than the second reference voltage, and wherein the second program verify voltage and the second reference voltage are greater than the first reference voltage and the first program verify voltage; determining in a second read operation that the second threshold voltage of the second memory cell has drifted down to between the first reference voltage and the second reference voltage; and in response to the determining in the second read operation, programming the second memory cell to increase the second threshold voltage of the second memory cell to meet or exceed the second program verify voltage.
10. 10. A semiconductor device, comprising: a plurality of memory cells formed on a semiconductor substrate; and control circuitry to: program a first memory cell of the plurality of memory cells to a first program state that is associated with a first program verify voltage and a first reference voltage such that the first memory cell has a first threshold voltage that meets or exceeds the first program verify voltage, wherein the first program verify voltage is greater than the first reference voltage; determine in a first read operation that the first threshold voltage of the first memory cell has drifted down to between the first program verify voltage and the first reference voltage; and in response to the determination in the first read operation, program the first memory cell to increase the first threshold voltage of the first memory cell to meet or exceed the first program verify voltage.
11. 11. The semiconductor device of claim 10, wherein the control circuitry to: determine the first memory cell is programmed to the first program state in a second read operation to determine the first threshold voltage of the first memory cell meets or exceeds the first reference voltage. 23 1616418352.1 Atty Dckt No.: 351918-981032 PATENT
12. 12. The semiconductor device of claim 10, wherein the determination in the first read operation comprises determine that the first threshold voltage of the first memory cell has drifted down to between a first refresh verify voltage and the first reference voltage, wherein the first refresh verify voltage is less than the first program verify voltage.
13. 13. The semiconductor device of claim 10, wherein the control circuitry to: program a second memory cell of the plurality of memory cells to a second program state that is associated with a second program verify voltage and a second reference voltage such that the second memory cell has a second threshold voltage that meets or exceeds the second program verify voltage and that is less than the first reference voltage, wherein the second program verify voltage is greater than the second reference voltage, and wherein the second program verify voltage and the second reference voltage are less than the first reference voltage; determine in a second read operation that the second threshold voltage of the second memory cell has drifted down to between the second program verify voltage and the second reference voltage; and in response to the determination in the second read operation, program the second memory cell to increase the second threshold voltage of the second memory cell to meet or exceed the second program verify voltage.
14. 14. The semiconductor device of claim 13, wherein the program of the first memory cell in response to the determination in the first read operation is performed before the program of the second memory cell in response to the determination in the second read operation.
15. 15. The semiconductor device of claim 13, wherein the control circuitry to: determine the second memory cell is programmed to the second program state in a third read operation to determine the second threshold voltage of the second memory cell meets or exceeds the second reference voltage and is lower than the first reference voltage. 24 1616418352.1 Atty Dckt No.: 351918-981032 PATENT
16. 16. The semiconductor device of claim 13, wherein the determination in the second read operation comprises determine that the second threshold voltage of the second memory cell has drifted down to between a second refresh verify voltage and the second reference voltage, wherein the second refresh verify voltage is less than the second program verify voltage.
17. 17. The semiconductor device of claim 13, wherein the first and second read operations are performed before the program of the first memory cell in response to the determination in the first read operation and the program of the second memory cell in response to the determination in the second read operation.
18. 18. The semiconductor device of claim 10, wherein the control circuitry to: program a second memory cell of the plurality of memory cells to a second program state that is associated with a second program verify voltage and a second reference voltage such that the second memory cell has a second threshold voltage that meets or exceeds the second program verify voltage, wherein the second program verify voltage is greater than the second reference voltage, and wherein the second program verify voltage and the second reference voltage are greater than the first reference voltage and the first program verify voltage; determine in a second read operation that the second threshold voltage of the second memory cell has drifted down to between the first reference voltage and the second reference voltage; and in response to the determination in the second read operation, program the second memory cell to increase the second threshold voltage of the second memory cell to meet or exceed the second program verify voltage.
19. 19. The semiconductor device of claim 10, wherein each of the plurality of memory cells comprises: a source region and a drain region formed in the semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region; and 25 1616418352.1 Atty Dckt No.: 351918-981032 PATENT a floating gate disposed over, for controlling a conductivity of, a first portion of the channel region.
20. 20. The semiconductor device of claim 19, wherein each of the plurality of memory cells comprises: a select gate disposed over, for controlling a conductivity of, a second portion of the channel region.

Description

Atty Dckt No.: 351918-981032 PATENT PROGRAM REFRESH FOR NON-VOLATILE MEMORY CELLS RELATED APPLICATIONS [0001] This application claims the benefit of U.S. Provisional Application No. 63/714,813, filed October 31, 2024, and, U.S. Patent Application No. 19/019,224, filed on January 13, 2025. FIELD OF THE INVENTION [0002] The present invention relates to non-volatile memory cells of semiconductor devices, and more particularly to a technique of programming memory cells. BACKGROUND OF THE INVENTION [0003] Split-gate non-volatile memory semiconductor devices are well known in the art. See for example U.S. Patent 7,868,375, which discloses a four-gate memory cell configuration, and which is incorporated herein by reference for all purposes. Specifically, Fig. 1 of the present disclosure illustrates a pair of split gate non-volatile memory cells 10 each with spaced apart source and drain regions 14/16 formed in a semiconductor substrate 12 (e.g., silicon). The source region 14 can be referred to as a source line SL (because it commonly is connected to other source regions for other non-volatile memory cells 10 in the same row or column), and the drain region 16 is commonly connected to a bit line. A channel region 18 of the semiconductor substrate 12 extends between the source/drain regions 14/16. A floating gate 20 is disposed over (i.e., vertically over and laterally overlapping) and insulated from (and directly controls the conductivity of) a first portion of the channel region 18 (and partially over, and insulated from, the source region 14). A control gate 22 is disposed over, and insulated from, the floating gate 20. A select gate 24 (also referred to as a word line gate) is disposed over, and insulated from, and directly controls the conductivity of, a second portion of the channel region 18. An erase gate 26 is disposed over and insulated from the source region 14 and is laterally adjacent to the floating gate 20. The erase gate 26 can include a notch that faces an edge of the floating gate 20. 1 1616418352.1 Atty Dckt No.: 351918-981032 PATENT [0004] A plurality of such memory cells 10 can be arranged in rows and columns to form a memory cell array, as illustrated in Fig. 2. While Fig. 1 only shows a pair of memory cells 10 (sharing a common source region 14 and erase gate 26), the memory cell pairs can be placed end to end to form a column of memory cells 10 (where the memory cell pairs can share a common drain region 16). While only two such columns are shown in Fig. 2, there can be many such columns. Each column can include a bit line 16a electrically connecting together all the drain regions 16 in the column. Each row of memory cells 10 can include a control gate line 22a electrically connecting together all the control gates 22 in the row of memory cells 10. For example, all the control gates 22 in each row of memory cells 10 can be formed as a continuous line of conductive material, where a portion of the continuous line passing through any given memory cell 10 serves as its control gate 22. Each row of memory cells 10 can include a select gate line 24a electrically connecting together all the select gates 24 in the row of memory cells 10. For example, all the select gates 24 in each row of memory cells 10 can be formed as a continuous line of conductive material, where a portion of the continuous line passing through any given memory cell 10 serves as its select gate 24. Each row of memory cell pairs can include an erase gate line 26a electrically connecting together all the erase gates 26 in the row of memory cell pairs. For example, all the erase gates 26 in each row of memory cell pairs can be formed as a continuous line of conductive material, where a portion of the continuous line passing through any given memory cell pair serves as its erase gate 26. Finally, each row of memory cell pairs can include a source line 14a electrically connecting together all the source regions 14 in the row of memory cell pairs. For example, all the source regions 14 in each row of memory cell pairs can be formed as a continuous line of conductive diffusion in the substrate 12, where a portion of the continuous line passing through any given memory cell pair serves as its source region 14. [0005] Various combinations of voltages are applied to the control gate 22, select gate 24, erase gate 26 and source and drain regions 14/16, to program the split gate non-volatile memory cell 10 (i.e., inject electrons onto the floating gate 20), to erase the split gate nonvolatile memory cell 10 (i.e., remove electrons from the floating gate 20), and to read the split gate non-volatile memory cell 10 (i.e., measure or detect the conductivity of the channel 2 1616418352.1 Atty Dckt No.: 351918-981032 PATENT region 18, by for example measuring or detecting a read current through the channel region 18, to determine the programming state of the floating gate 20). [0006] Split gate non-volatile memory cell 10 can be operated in