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WO-2026095972-A1 - TEMPERATURE COMPENSATION FOR ANALOG MEMORY CELLS IN A NEURAL NETWORK

WO2026095972A1WO 2026095972 A1WO2026095972 A1WO 2026095972A1WO-2026095972-A1

Abstract

In one example, a method comprises determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal; and applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.

Inventors

  • VU, HOA
  • HONG, STANLEY
  • TRAN, HIEU VAN
  • VU, THUAN
  • TRINH, STEPHEN

Assignees

  • SILICON STORAGE TECHNOLOGY, INC.

Dates

Publication Date
20260507
Application Date
20250128
Priority Date
20241219

Claims (20)

  1. 1. A method comprising: determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal; and applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.
  2. 2. The method of claim 1, wherein the non-volatile memory cells are split-gate flash memory cells.
  3. 3. A circuit to generate a control gate and erase gate bias voltage, comprising: a reference memory cell comprising a control gate terminal, an erase gate terminal, and a bit line terminal; a current digital-to-analog converter to generate a current in response to a digital input and to apply the current to the bit line terminal; and an operational amplifier comprising an inverting terminal coupled to a bit line, a noninverting terminal coupled to a reference voltage, and an output terminal providing a voltage to the control gate terminal and the erase gate terminal, wherein the voltage is output from the circuit as the control gate and erase gate bias voltage.
  4. 4. The circuit of claim 3, wherein the current digital-to-analog converter generates the current in response to a digital input.
  5. 5. The circuit of claim 3, further comprising a row driver comprising: a PMOS transistor comprising a first terminal coupled to receive the control gate and erase gate bias voltage, a gate to receive a first control signal, and a second terminal; a first NMOS transistor comprising a first terminal coupled to the second terminal of the PMOS transistor at a node, a gate to receive the first control signal, and a second terminal coupled to ground; a second NMOS transistor comprising a first terminal coupled to the node, a gate to receive a second control signal, and a second terminal coupled to a control gate line of a row of cells in an array; and 25 1616646849 1 Attorney Docket Number: 351913-981042 a third NMOS transistor comprising a first terminal coupled to the node, a gate to receive the second control signal, and a second terminal coupled to an erase gate line of the row.
  6. 6. A method comprising: determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal; and applying voltages based on the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.
  7. 7. The method of claim 6, wherein the applying voltages is performed by a global digital-to-analog converter.
  8. 8. The method of claim 6, wherein the applying voltages is performed by a row decoder.
  9. 9. A method comprising: conducting a bias current through a reference memory cell; generating a bias voltage based on the bias current; and applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell during a read operation.
  10. 10. The method of claim 9, wherein the applying comprises applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell.
  11. 11. The method of claim 9, wherein the applying is performed by a global digital-to- analog converter.
  12. 12. A method comprising: deriving a bias voltage from a combined control gate and erase gate temperature compensated voltage; and providing the bias voltage to control gate terminals and erase gate terminals of selected memory cells during a read operation.
  13. 13. The method of claim 12, wherein the providing is performed by a global digital- to-analog converter. 26 1616646849 1 Attorney Docket Number: 351913-981042
  14. 14. The method of claim 12, comprising coupling the control gate terminals and erase gate terminals of the selected memory cells to ground when the selected memory cells are not selected for a read operation.
  15. 15. A system comprising: an array of non-volatile memory cells arranged into rows and columns, each of the nonvolatile memory cells comprising a control gate terminal and an erase gate terminal, wherein the control gate terminal of each non-volatile memory cell in a row is coupled to a control gate line and the erase gate terminal of each non-volatile memory cell in a row is coupled to an erase gate line; and a plurality of row circuits, each row circuit applying a voltage to a control gate line and an erase gate line coupled to a row of the array during a read operation of one or more nonvolatile memory cells in the row.
  16. 16. The system of claim 15, wherein the voltage is generated by a global digital -to- analog converter shared by the plurality of row circuits.
  17. 17. The system of claim 16, wherein the global digital -to-analog converter generates the voltage based on a plurality of reference voltages.
  18. 18. The system of claim 17, wherein the plurality of reference voltages are generated in response to a combined control gate and erase gate bias voltage.
  19. 19. The system of claim 15, wherein each row circuit comprises a pulse generator to generate the voltage.
  20. 20. The system of claim 15, wherein each row circuit comprises a driver to generate the voltage. 27 1616646849 1

Description

Attorney Docket Number: 351913-981042 TEMPERATURE COMPENSATION FOR ANALOG MEMORY CELLS IN A NEURAL NETWORK PRIORITY CLAIM [0001] This application claims priority to U.S. Provisional Patent Application No. 63/716,166, filed on November 4, 2024, and titled “Temperature Compensation for Analog Memory Cells in a Neural Network,” and U.S. Patent Application No. 18/988,841, filed on December 19, 2024, and titled “Temperature Compensation for Analog Memory Cells in a Neural Network.” FIELD OF THE INVENTION [0002] Numerous examples are disclosed for providing temperature compensation for analog memory cells used in a neural network. BACKGROUND OF THE INVENTION [0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. Artificial neural networks generally include layers of interconnected "neurons" which exchange messages between each other. [0004] Figure 1 illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses. [0005] One of the major challenges in the development of artificial neural networks for high- performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e., a very high computational parallelism. In principle, such complexity can be 1 1616646849 1 Attorney Docket Number: 351913-981042 achieved with digital supercomputers or graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low- precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses. [0006] Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in U.S. Patent Application Publication 2017/0337466A1, which is incorporated by reference. The non-volatile memory arrays operate as an analog neural memory and comprise non-volatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. Non-Volatile Memory Cells [0007] Non-volatile memories are well known. For example, U.S. Patent 5,029,130 (“the ’ 130 patent”), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes source region 14 and drain region 16 formed in semiconductor substrate 12, with channel region 18 there between. Floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14. Word line terminal 22 (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion that extends up 2 1616646849 1 Attorney Docket Number: 351913-981042 and over the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide. Bitline 24 is coupled to drain region 16. [0008] Memory cell 210