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WO-2026096111-A1 - SILICON INTERPOSER WITH INTEGRATED VOLTAGE REGULATOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS

WO2026096111A1WO 2026096111 A1WO2026096111 A1WO 2026096111A1WO-2026096111-A1

Abstract

Voltage regulator devices on active silicon interposers and associated systems and methods are disclosed. Local High-Bandwidth Memory (HBM) device voltage regulation is provided via the active silicon interposer configured with one or more voltage regulators corresponding to one or more HBM devices of a system-in-package (SiP). Each of the voltage regulators are configured to receive a first voltage signal from an external power supply and to generate one or more voltage signals based on the first voltage signal. The one or more generated voltage signals are supplied to a given HBM device by a locally positioned voltage regulator. In some embodiments, the one or more generated voltage signals are further based on the voltage signal of a sense line coupling a given HBM device to a corresponding voltage regulator.

Inventors

  • KARIYA, Rajesh, H.

Assignees

  • MICRON TECHNOLOGY, INC.

Dates

Publication Date
20260507
Application Date
20250919
Priority Date
20241030

Claims (20)

  1. 1. A system-in-package (SiP) device configured with local voltage regulation, the SiP device comprising: a package substrate comprising: a first surface; a second surface opposite the first surface; and at least one solder ball coupled to the first surface, the at least one solder ball configured to receive a first voltage signal supplied by an external power supply; an active silicon interposer carried by the package substrate and positioned on the second surface of the package substrate, the active silicon interposer comprising: a voltage regulator configured to: receive the first voltage signal from the external power supply via the at least one solder ball; and generate a second voltage signal based on the first voltage signal; and a high-bandwidth memory (HBM) device carried by the active silicon interposer, the HBM device comprising: an interface die comprising a power supply input/output (IO) circuit, the power supply IO circuit configured to receive the second voltage signal generated by the voltage regulator; and one or more volatile memory dies carried by the interface die.
  2. 2. The SiP device of claim 1, wherein the second voltage signal generated by the voltage regulator and the first voltage signal are a same voltage.
  3. 3. The SiP device of claim 1, wherein the second voltage signal generated by the voltage regulator is a different voltage from the first voltage signal.
  4. 4. The SiP device of claim 1, wherein the voltage regulator is further configured to generate a third voltage signal based on the first voltage signal, the third voltage signal being a Attomey Docket No. P329509.W0.01 Client Ref. No.: 2024148637-WO-PCT different voltage than the second voltage signal, and wherein the power supply IO circuit of the HBM device is further configured to receive the third voltage signal generated by the voltage regulator.
  5. 5. The SiP device of claim 1, further comprising a sense line, the sense line generated by the HBM device and received by the voltage regulator, wherein the voltage regulator is further configured to modify the second voltage signal in response to a voltage of the sense line.
  6. 6. The SiP device of claim 1, further comprising a direct access (DA) line coupled to a solder ball of the package substrate and the voltage regulator, the voltage regulator further configured to modify the second voltage signal based on input from the DA line.
  7. 7. The SiP device of claim 1, further comprising: a second solder ball coupled to the first surface of the package substrate, the second solder ball configured to receive a third voltage signal supplied by the external power supply; a second voltage regulator of the active silicon interposer, the second voltage regulator configured to: receive the third voltage signal from the external power supply via the second solder ball; and generate a fourth voltage signal based on the third voltage signal; and a second HBM device carried by the active silicon interposer, the second HBM device configured to receive the third voltage signal generated by the second voltage regulator.
  8. 8. The SiP device of claim 7, wherein the first voltage signal generated by the external power supply and the third voltage signal generated by the external power supply are a same voltage.
  9. 9. The SiP device of claim 7, wherein the first voltage signal generated by the external power supply and the third voltage generated by the external power supply are different voltages. Attomey Docket No. P329509.W0.01 Client Ref. No.: 2024148637-WO-PCT
  10. 10. The SiP device of claim 7, wherein the second voltage signal generated by the first voltage regulator and the fourth voltage signal generated by the second voltage regulator are a same voltage.
  11. 11. The SiP device of claim 7, wherein the second voltage signal generated by the first voltage regulator and the fourth voltage signal generated by the second voltage regulator are different voltages.
  12. 12. The SiP device of claim 7, wherein the first, second, third, and fourth voltage signals are each different voltages from each other.
  13. 13. The SiP device of claim 7, wherein the power supply IO circuit for the first HBM device comprises a first power IO port, the power supply IO circuit for the second HBM device comprises a second power IO port, and both the first power IO port and second power IO port are configured to receive a power signal corresponding to a baseline voltage, and wherein: the first power IO port is coupled to the second voltage signal, the second voltage signal associated with a voltage different from the baseline voltage; and the second power IO port is coupled to the fourth voltage signal, the fourth voltage signal associated with a voltage different from the baseline voltage.
  14. 14. The SiP device of claim 13, wherein the second voltage signal is less than the baseline voltage, and wherein the fourth voltage signal is less than the baseline voltage.
  15. 15. The SiP device of claim 13, wherein the second voltage signal is greater than the baseline voltage, and wherein the fourth voltage signal is greater than the baseline voltage.
  16. 16. The SiP device of claim 13, wherein the second voltage signal is greater than the baseline voltage, and wherein the third voltage signal is less than the baseline voltage.
  17. 17. The SiP device of claim 1, further comprising a host device carried by the active silicon interposer, the host device positioned adjacent to the first HBM device and communicably coupled to the first HBM device. Attorney Docket No. P329509.W0.01 Client Ref. No.: 2024148637-WO-PCT
  18. 18. An HBM voltage regulation device comprising: a printed circuit board (PCB) comprising at least one solder ball, the at least one solder ball configured to receive a first voltage signal supplied by an external power supply; and an active silicon interposer carried by the PCB, the active silicon interposer comprising: a voltage regulator configured to: receive the first voltage signal from the external power supply via the at least one solder ball; generate a second voltage signal based on the first voltage signal; supply the second voltage signal to an HBM device; receive a voltage from a sense line generated by the HBM device; and modify the second voltage signal based on the voltage of the sense line.
  19. 19. The HBM voltage regulation device of claim 18, wherein the voltage regulator is further configured to generate a third voltage signal based on the first voltage signal, the third voltage signal being a different voltage than the second voltage signal, and wherein the voltage regulator is further configured to supply the third voltage signal to the HBM device.
  20. 20. The HBM voltage regulation device of claim 18, further comprising: a second solder ball of the PCB configured to receive a third voltage signal supplied by the external power supply; and a second voltage regulator of the active silicon interposer, the second voltage regulator configured to: receive the third voltage signal from the external power supply via the second solder ball; generate a fourth voltage signal based on the third voltage signal; supply the fourth voltage signal to a second HBM device; receive a voltage from a sense line generated by the second HBM device; and modify the fourth voltage signal based on the voltage of the sense line.

Description

Attorney Docket No. P329509.W0.01 Client Ref. No.: 2024148637-WO-PCT SILICON INTERPOSER WITH INTEGRATED VOLTAGE REGULATOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS CROSS-REFERENCE TO RELATED APPLICATION(S) [0001] The present application claims priority to U.S. Provisional Patent Application No. 63/713,705, filed October 30, 2024, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD [0002] The present technology is generally related to regulating the voltage of semiconductor devices, and more specifically to systems and methods for interposers with integrated voltage regulators that regulate the voltages of high-bandwidth memory devices and other devices of a system-in-package. BACKGROUND [0003] An electronic apparatus (e.g., a processor, a memory device, a memory system, or a combination thereof) can include one or more semiconductor circuits configured to store and/or process information. For example, the apparatus can include a memory device, such as a volatile memory device, a non-volatile memory device, or a combination device. Memory devices, such as dynamic random-access memory (DRAM) and/or high-bandwidth memory (HBM), can utilize electrical energy to store and access data. [0004] With technological advancements in embedded systems and increasing applications, the market is continuously looking for faster, more efficient, and smaller devices. To meet market demands, semiconductor devices are being pushed to the limit with various improvements. Improving devices, generally, may include increasing circuit density, increasing circuit capacity, increasing operating speeds (or otherwise reducing operational latency), increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Attempts, however, to meet market demands, such as simplifying circuit design and streamlining operability, can often introduce challenges in other aspects. Attomey Docket No. P329509.W0.01 Client Ref. No.: 2024148637-WO-PCT BRIEF DESCRIPTION OF THE DRAWINGS [0005] Figure 1 is a partially schematic cross-sectional diagram of a system-in-package (SiP) device. [0006] Figure 2 is a partially schematic cross-sectional diagram of a SiP device. [0007] Figure 3 is a partially schematic cross-sectional diagram of a SiP device with an active interposer configured in accordance with some embodiments of the present technology. [0008] Figure 4 is a flow diagram of a process for manufacturing a SiP device in accordance with some embodiments of the present technology. [0009] The drawings have not necessarily been drawn to scale. Similarly, some components and/or operations can be separated into different blocks or combined into a single block for the purpose of discussion of some of the implementations of the present technology. Moreover, while the technology is amenable to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and are described in detail below. The intention, however, is not to limit the technology to the particular implementations described. DETAILED DESCRIPTION [0010] High data reliability, high speed of memory access, lower power consumption, and reduced chip size are features that are demanded from semiconductor memory. In recent years, vertically stacked memory devices have been introduced, often referred to as 2.5 -dimensional (“2.5D”) memory devices when placed adjacent to a host device. Some 2.5D memory devices are formed by stacking memory dies vertically, and interconnecting the dies using through-silicon (or through-substrate) vias (TSVs). Benefits of the 2.5D memory devices include shorter interconnects (which reduce circuit delays and power consumption), a large number of vertical vias between layers (which allow wide bandwidth buses between functional blocks, such as memory dies, in different layers), and a considerably smaller footprint. Thus, the 2.5D memory devices contribute to higher memory access speed, lower power consumption, and chip size reduction. Example 2.5D memory devices include Hybrid Memory Cube (HMC) and High- Bandwidth Memory (HBM) devices. For example, HBM devices are a type of memory that includes a vertical stack of dynamic random-access memory (DRAM) dies and an interface die (which, e.g., provides the interface between the DRAM dies of the HBM device and a host device). Attomey Docket No. P329509.W0.01 Client Ref. No.: 2024148637-WO-PCT As a further example, HBM devices can include a combination of different volatile and/or nonvolatile memory types. [0011] In a system-in-package (SiP) configuration, HBM devices may be integrated with host devices (e.g., one or more graphics processing units (GPUs), computer processing units (CPUs), tensor processing units (TCUs), and/or any other suitable processing units) using a base substrate (e.g., a silicon interposer, a substrate of organic material, a substrate of inorga