WO-2026096793-A1 - IN-PLANE 2D TELLURIDE HETERO-PHASE STRUCTURES AND METHODS FOR FABRICATION

Abstract

A device includes a substrate, an insulator, a first semimetallic 1T' phase telluride portion, a semiconducting 2H phase telluride portion, and a second semimetallic 1T' phase telluride portion. The insulator is on the substrate. The first semimetallic 1T' phase telluride portion is on the insulator. The semiconducting 2H phase telluride portion is on the insulator and seamlessly connected at the atomic level to the first semimetallic 1T' phase telluride portion. The second semimetallic 1T' phase telluride portion is on the insulator and spaced apart from the first semimetallic 1T' phase telluride portion and seamlessly connected at the atomic level to the semiconducting 2HI phase telluride portion.

Inventors

• ZHU, WENJUAN
• LEE, Hanwool
• LIN, Ye
• ZHENG, JUN-FEI

Assignees

• ENTEGRIS, INC.
• THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS

Dates

Publication Date

20260507

Application Date

20251030

Priority Date

20241030

Claims (20)

1. What is claimed is:
2. 1. A device comprising:
3. a substrate;
4. an insulator on the substrate;
5. a first semimetallic IT' phase telluride portion on the insulator;
6. a semiconducting 2H phase telluride portion on the insulator and seamlessly connected at the atomic level to the first semimetallic IT' phase telluride portion, and a second semimetallic IT' phase telluride portion on the insulator and spaced apart from the first semimetallic IT' phase telluride portion and seamlessly connected at the atomic level to the semiconducting 2H phase telluride portion.
7. 2. The device of claim 1, wherein the semimetallic IT' phase telluride comprises molybdenum ditelluride (MoTe2), tungsten telluride (WTe?), molybdenum tungsten telluride (Mo x W 1−x Te 2 ), tungsten selenium telluride (WSe2 X -2 X Te2 X ), or tungsten sulfur telluride (WSe2 X -2 X Te2 X ).
8. 3. The device of claim 1, wherein the semiconducting 2H phase telluride comprises molybdenum ditelluride (MoTe2), molybdenum tungsten telluride (Mo x W 1−x Te 2 ), molybdenum selenium telluride (MoSe2 X -2 X Te2 X ), molybdenum sulfur telluride (MoSe2 X -2 X Te2x), tungsten selenium telluride (WSe2 X -2 X Te2 X ), or tungsten sulfur telluride (WSe2 X -2xTe2x).
9. 4. The device of claim 1, further comprising:
10. a first metal electrode contacting the first semimetallic IT' phase telluride portion; and
11. a second metal electrode contacting the second semimetallic IT' phase telluride portion.
12. 5. The device of claim 1, further comprising:
13. a gate insulator on the semiconducting 2H phase telluride portion; and a gate electrode on the gate insulator. 6. The device of claim 1, wherein the semiconducting 2H phase telluride portion comprises an n-type doped region and a p-type doped region forming a p-n junction.
14. 7. The device of claim 6, wherein the first semimetallic IT' phase telluride portion contacts the n-type region and comprises a first work function, and
15. wherein the second semimetallic IT' phase telluride portion contacts the p-type region and comprises a second work function.
16. 8. The device of claim 1, further comprising:
17. a tunnel insulator on the semiconducting 2H phase telluride portion;
18. a floating gate or charge trapping layer on the tunnel insulator;
19. a gate insulator on the floating gate or charge trapping layer;
20. a gate electrode on the gate insulator;

Description

IN-PLANE 2D TELLURIDE HETERO PHASE STRUCTURES AND METHODS FOR FABRICATION Cross-reference to Related Application [0001] This application claims the benefit of and priority to United States Provisional Application No. 63/713,821 filed on October 30, 2024, the contents of which are incorporated herein by reference in their entirety for all purposes. Field [0002] The present disclosure relates generally to in-plane 2D telluride hetero-phase structures and methods for fabrication. In particular, the present disclosure relates to in-plane 2D telluride hetero-phase structures fabricated by simultaneously forming a semimetallic IT' phase telluride portion seamlessly connected at the atomic level to a semiconducting 211 phase telluride portion. Background [0003] Typical transistors with 2D material channels are Schottky barrier transistors, which have large contact resistance due to high Schottky barrier, atomically thin body, and Fermi level pinning. This high contact resistance significantly limits current injection efficiency and overall device performance, especially at low operating voltages. Moreover, the lack of robust doping strategies and the sensitivity of 2D materials to interface states further exacerbate the challenge of achieving low-resistance contacts. Summary [0004] It has been demonstrated that employing a 1T'/2H phase heterojunction may significantly reduce contact resistance in MoTe2 2D transistors. One suggested fabrication method for MoTe2 2D transistors involves using a laser to induce phase change in specific areas of the 2H MoTe2 flake, thereby creating a 1T'/2H MoTe2 heterojunction. This method, however, fails to ensure good crystallinity in the IT' MoTe2 contact region and does not support large-scale fabrication. Alternatively, some studies have shown that a 1T'/2H MoTe2 heterojunction may be formed during a chemical vapor deposition (CVD) process by controlling reaction parameters such as duration and temperature, which results in low contact resistance. However, the random determination of the position and dimensions of the IT' and 2H phase MoTe2 regions during the synthesis makes these approaches impractical for very large scale integrated (VLSI) device fabrication. Other approaches include multi-step processes such as transferring IT’ contacts onto the 2H phase M0TC2 or using CVD twice to fomi the 2H and IT’ phase MoTe2 regions, both of which complicate the fabrication process. [0005] The in-plane 2D telluride hetero-phase structures disclosed herein effectively reduce the contact resistance while maintaining a high on/off ratio by taking advantage of the semiconducting nature of the 2H phase and the semimetallic properties of the IT’ phase. The hetero-phase structures may be used for high performance logic transistors, memories, photo detectors, etc., where the IT’ phase transition metal dichalcogenide (TMD) serves as the source and drain contacts, while the 2H phase TMD serves as the channel. The methods disclosed herein simplify the fabrication process for in-plane 2D telluride hetero-phase structures, allow for large-scale production, and provide precise control over the position and dimensions of the devices, facilitating a scaling down of the device size. By addressing the issue of large contact resistance, the current disclosure enhances the commercial viability of 2D transistors and resolves a significant challenge in 2D transistor technology. [0006] Some examples of the present disclosure relate to a device. The device includes a substrate, an insulator, a first semimetallic IT’ phase telluride portion, a semiconducting 2H phase telluride portion, and a second semimetallic IT’ phase telluride portion. The insulator is on the substrate. The first semimetallic IT’ phase telluride portion is on the insulator. The semiconducting 2H phase telluride portion is on the insulator and seamlessly connected at the atomic level to the first semimetallic IT’ phase telluride portion. The second semimetallic IT' phase telluride portion is on the insulator and spaced apart from the first semimetallic IT' phase telluride portion and seamlessly connected at the atomic level to the semiconducting 2H phase telluride portion. [0007] Other examples of the present disclosure relate to a method for fabricating an in-plane 2D telluride hetero-phase structure. The method includes forming an insulating layer on a substrate. The method includes forming a first metal portion and a second metal portion spaced apart from the first metal portion on the insulating layer such that a portion of the insulating layer is exposed directly between the first metal portion and the second metal portion. The method includes simultaneously converting the first metal portion and the second metal portion to a semimetallic IT' phase telluride while forming a semiconducting 2H phase telluride on the exposed portion of the insulating layer between the first metal portion and the second metal portion. [0008] Additional