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WO-2026096870-A1 - DIFFERENTIAL CLOCK SIGNAL ADJUSTMENT

WO2026096870A1WO 2026096870 A1WO2026096870 A1WO 2026096870A1WO-2026096870-A1

Abstract

Methods, devices, and systems for clock circuit correction. In one aspect, a circuit includes a first input configured to receive a first signal and a second input configured to receive a second signal. The circuit includes a first line coupled to the first input, the first line includes a plurality of first inverters and a second line coupled to the second input, the second line includes a plurality of second inverters. The circuit includes a crossover circuit coupled to the first line at a first node and the second line at a second node. The crossover circuit generates a first correction signal with the first signal from the first node passing through a crossover inverter within the crossover circuit and provides the first correction signal to the second node on the second line to correct the second signal.

Inventors

  • YASOTHARAN, HEMESH
  • MISHRA, PARMANAND

Assignees

  • SICILY MERGER SUB II, INC

Dates

Publication Date
20260507
Application Date
20251031
Priority Date
20241101

Claims (20)

  1. 1. A circuit compri sin : a first input configured to receive a first signal; a second input configured to receive a second signal; a first line coupled to the first input, wherein the first line comprises a plurality of first inverters; a second line coupled to the second input, wherein the second line comprises a plurality of second inverters; and a crossover circuit coupled to the first line at a first node and the second line at a second node, wherein the crossover circuit is configured to: generate a first correction signal with the first signal from the first node passing through a crossover inverter within the crossover circuit; and provide the first correction signal to the second node on the second line to correct the second signal.
  2. 2. The circuit of claim 1, wherein the crossover circuit comprises: a plurality of switches configured to couple the crossover circuit to the first line at the first node and to the second line at the second node; and a matrix bus configured to set positions of the plurality of switches to select the first node and the second node.
  3. 3. The circuit of claim 1, wherein the circuit comprises: a plurality of first nodes along the first line, wherein each first node of the plurality of first nodes is positioned as an input to a corresponding first inverter of the plurality of first inverters; and a plurality of second nodes along the second line, wherein each second node of the plurality of second nodes is positioned as an input to a corresponding second inverter of the plurality of second inverters.
  4. 4. The circuit of claim 1, wherein the circuit comprises: a first output connected to an output of the first line; and Attorney Docket No. 07136-0126WO1 a second output connected to an output of the second line.
  5. 5. The circuit of claim 4, wherein the circuit comprises: a controller coupled to the first output from the first line and the second output from the second line, wherein the controller is configured to: measure a difference between the first output and the second output; determine whether the difference between the first output and the second output satisfies a differential threshold; and in response to determining the difference between the first output and the second output does not satisfy the different threshold, determine a desired adjustment to at least one of the first output or the second output.
  6. 6. The circuit of claim 5, wherein determining the desired adjustment to at least one of the first output or the second output, the circuit is configured to: determine a delay between the first output and the second output; select a configuration of the plurality of switches in the crossover circuit such that the correction signal generated from the first node and provided to the second node compensates for the determined delay, wherein the configuration of the plurality of switches is based on the crossover inverter and at least one of (i) a first inverter of the plurality of first inverters or (ii) a second inverter of the plurality of second inverters.
  7. 7. The circuit of claim 5, wherein the controller is configured to dynamically adjust at least one of (i) a drive strength of the crossover inverter or (ii) a configuration of a plurality of switches in the crossover circuit.
  8. 8. The circuit of claim 7, wherein the controller is configured to dynamically adjust at least one of (i) the drive strength of the crossover inverter or (ii) the configuration of a plurality of switches in the crossover circuit based on at least one of time, skew, or phase discrepancies between the first output and the second output. Attorney Docket No. 07136-0126WO1
  9. 9. The circuit of claim 5, wherein determining the difference between the first output and the second output comprises the circuit is configured to determine a slope of a voltage change of the first output and the second output.
  10. 10. The circuit of claim 5, wherein the controller is configured to monitor at least one of an edge slope, a deviation in duty cycle, or a phase skew of the first output and the second output.
  11. 11. The circuit of claim 10, wherein the circuit is configured to assign a configuration of the crossover circuit in response to detecting at least one of the edge slope, the deviation in duty cycle, or the phase skew of the first output and the second output do not satisfy a threshold value.
  12. 12. The circuit of claim 1, wherein the crossover inverter in the crossover circuit is configured to perform duty cycle correction and inter-symbol inference (ISI) equalization.
  13. 13. The circuit of claim 1, wherein the crossover inverter is configured to provide pre-tap equalization by generating the first correction signal based on a delayed and inverted version of the first signal from the first node.
  14. 14. The circuit of claim 1, wherein the crossover inverter comprises a programmable driver that is controlled by a set of digital control bits, the set of digital control bits configures the crossover inverter for a drive level strength of the first correction signal.
  15. 15. A method comprising: receiving a first signal at a first input; receiving a second signal at a second input; propagating the first signal along a first line, the first line comprising a plurality of first inverters; propagating the second signal along a second line, the second line comprising a plurality of second inverters; Attorney Docket No. 07136-0126WO1 generating, at a crossover circuit coupled between the first line at a first node and the second line at a second node, a first correction signal by processing the first signal from the first node passing through a crossover circuit within the crossover circuit; and providing the first correction signal to the second node on the second line to correct the second signal.
  16. 16. The method of claim 15, further comprising: coupling the crossover circuit to the first line at the first node and to the second line at the second node using a plurality of switches; and setting positions of the plurality of switches to select the first node and the second node using a matrix bus.
  17. 17. The method of claim 15, wherein the first line comprises a plurality of first nodes, each first node of the plurality of first nodes is positioned as an input to a corresponding first inverter of the plurality of first inverters.
  18. 18. The method of claim 15, wherein the second line comprises a plurality of second nodes along the second line, each second node of the plurality of second nodes is positioned as an input to a corresponding second inverter of the plurality of second inverters.
  19. 19. The method of claim 15, wherein the first line comprises a first output and the second line comprises a second output.
  20. 20. The method of claim 15, further comprising: measuring, using a controller that is coupled to the first output from the first line and the second output from the second line, a difference between the first output and the second output; determining whether the difference between the first output and the second output satisfies a differential threshold; and in response to determining the difference between the first output and the second output does not satisfy the different threshold, determining a desired adjustment to at least one of the first output or the second output.

Description

Attorney Docket No. 07136-0126WO1 DIFFERENTIAL CLOCK SIGNAL ADJUSTMENT CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to Provisional Application No. 18/934,986, originally filed as a Non-Provisional Application on November 1, 2024, titled “Methods and Systems for Adjusting Differential Clock Signals,” previously assigned Serial No. 18/934,986, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD This specification generally relates to electrical circuits, and more specifically, adjusting a differential clock signal in electrical circuits. BACKGROUND In high-speed communication systems and other digital applications, the integrity and timing of clock signals are crucial for ensuring accurate data transmission and reception. Clock signals serve as a timing reference that coordinates a sequence of operations within electronic circuits, such as data sampling, data processing, data transmission, and data reception. In many modern, data can be transmitted as differential signals, where a pair of clock signals are used to reduce noise and improve signal integrity. However, in practice, these pair of clock signals are often subject to various forms of degradation as these signals propagate through a circuit. These forms of degradation can include, for example, phase misalignment, inter-symbol interference, and jitter, to name a few examples. SUMMARY To address degradation of differential clock signals in electrical circuits, the techniques described in this application perform various functions to adjust or correct for degradation in the differential clock signals. By adjusting or correcting the clock signal, such as correcting its timing, skew, amplitude, or other characteristics, the differential signals remain synchronized and ensure that the overall system performance is well maintained. By correcting skew misalignments, duty cycle distortions, and other forms of degradation, clock signal improves the reliability and accuracy of high-speed communication systems. Attorney Docket No. 07136-0126WO1 In some implementations, the specification can provide apparatus, systems and techniques of a clock compensation device that is configured to correct timing discrepancies in differential clock signals. The clock compensation device includes various components that work collectively to generate correction signals to ensure that the differential clock signals maintain synchronization with one another. For example, the clock compensation device can include a position line and a negative line. Each circuit line in the clock compensation device includes various inverters that introduces a specific delay on the signal and flips a logical value of the signal, e g., flips the signal from a logical “1” of high to a logical “0” of low or flights the signal from a logical “0” to a logical “1”. In some implementations, the clock compensation device can utilize the signals from the positive line to correct delays detected on the negative line. Similarly, the clock compensation device can utilize the signals from the negative line to correct delays detected on the positive line. In this manner, the differential clock signals remain synchronized according to their respective components. The clock compensation device can be configured, on the fly, to introduce correction signals from the positive line to the negative line or vice versa, depending on the signal of the differential clock signal that is delayed or skewed. For example, the clock compensation device can continuously measure clock synchronization between the differential clock signals. If the clock compensation device measures or detects a delay or particular delta between the differential clock signals, the clock compensation device can configure a crossover circuitry between the positive line and negative line to generate and inject appropriate correction signals one or more of the lines causing the delay. As will be further described below, the clock compensation device can configure one or more inverters in the crossover circuitry to connect in different configurations to reduce or remove the detected delay. Once the crossover circuitry is configured in the manner that will retain synchronization between the differential clock signals, then the signal from one line will be passed to the other line according to the configuration. In this instance, the clock compensation device corrects the delay by injecting one or more signals from one line, e.g., the corrected signal, at a particular node on the other line. The injection of correction signals at a particular node can remove the delay by summing opposite and time delayed signals. The summation of the opposite and time delayed signals results in one Attorney Docket No. 07136-0126WO1 of the signals removing their overall delay, and correcting time synchronization between the differential clock signals. In one general aspect, a circuit includes: a first input conf