WO-2026096996-A1 - AUTOMATIC SWITCHING BETWEEN TWO TYPES OF INTERFACE DEVICES ON PARALLEL DATA BUSES

WO2026096996A1WO 2026096996 A1WO2026096996 A1WO 2026096996A1WO-2026096996-A1

Abstract

Automatic Switching Between Two Types of Interface Devices on Parallel Data Buses Various aspects of the disclosed technology relate to automatic switching between two types of interface devices on a data streaming network. The first type of interface devices can enter a sleep mode in response to a unique command data packet and sleep for a number of clock cycles specified in the unique command data packet (1230). The second type of interfaces devices can be activated by a sentinel signal and then process data transmitted in the data streaming network while the first type of interfaces is in the sleep mode (1240, 1250). After completing processing the data, the second type of interfaces devices become deactivated, and the first type of interfaces exits the sleep mode to process data transmitted in the data streaming network (1260). The process can be repeated.

Inventors

COTE, JEAN-FRANCOIS
STEPNIEWSKA, Marta
BURCHARD, Jan
KAMPMANN, MATTHIAS

Assignees

SIEMENS INDUSTRY SOFTWARE INC.

Dates

Publication Date: 20260507
Application Date: 20251103
Priority Date: 20241101

Claims (9)

1. A circuit, comprising: a first network comprising multiple data channels configured to transmit data in parallel in the circuit and circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of circuit blocks in the circuit; a plurality of second networks, each of the plurality of second networks comprising a local serial network configured to transmit data serially in one of the circuit blocks in the circuit; a third network configured to transmit data serially in the circuit; and a plurality of network switching interface devices, each of the plurality of network switching interface devices being associated with one of the circuit blocks and configured_to couple either the first network or the third network to one of the plurality of second networks based on a control signal stored in a register in the each of the plurality of network switching interface devices, wherein when the first network is coupled to the one of the plurality of second networks based on the control signal, the each of the plurality of network switching interface devices is configured to: enter, based on a unique command data packet received from the first network, a sleep mode in which the each of the plurality of network switching interface devices is configured to not process data transmitted in the first network and to block a communication path between the one of the plurality of second networks and the first network, remain in the sleep mode for a number of clock cycles specified in the unique command data packet, and 202419433 exit the sleep mode, and wherein during the sleep mode, one or more circuit block interface devices that are activated among the circuit block interface devices are configured to allow corresponding circuit blocks to communicate with the first network, the activation of the one or more circuit block interface devices being based on configuration data received from a combination of the first network and corresponding second networks and subsequently on a further activation signal received from the first network.
2. The circuit recited in claim 1, wherein the control signal stored in the each of the plurality of network switching interface devices is received from the third network.
3. The circuit recited in claim 1, wherein the third network and the plurality of second networks conform to the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group).
4. The circuit recited in claim 3, wherein the unique command data packet comprises a unique sequence of TMS (test mode select) bits causing a TAP (test access port) finite-state machine to enter a sequence not used for normal packets and bits specifying the number of clock cycles for the sleep mode.
5. The circuit recited in claim 3, wherein during the sleep mode, the each of the plurality of network switching interface devices is configured to prevent, a locally generated clock signal 202419433 from reaching the one of the plurality of second networks, a TMS signal from reaching a TAP finite-state machine, or both.
6. A method, comprising: A: transmitting, via a third network in a circuit, configuration data to a plurality of network switching interface devices, wherein the third network is configured to transmit data serially in the circuit, and wherein each of the plurality of network switching interface devices is associated with one of circuit blocks in the circuit, the configuration data comprising a control signal causing a plurality of second networks to change from being coupled to the third network to being coupled to a first network, wherein each of the plurality of second networks comprises a local serial network configured to transmit data serially in one of the circuit blocks, and wherein the first network comprises multiple data channels configured to transmit data in parallel in the circuit and circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of the circuit blocks; B: transmitting, via the first network, setup data to the plurality of second networks, the setup data comprising test setup data for one or more of the circuit blocks and configuration data for configuring and enabling one or more of the circuit block interface devices; C: transmitting, via the first network, a unique command data packet to cause the plurality of network switching interface devices to enter a sleep mode in which the plurality of network switching interface devices are configured to not process data transmitted in the first network and to block communication paths between the plurality of second networks and the first network; 202419433 D: transmitting, via the first network, a further activation signal to cause the one or more of the circuit block interface devices to be ready for communication between the first network and the one or more of the circuit blocks; E: transmitting, via the first network, test data to the one or more of the circuit blocks; F: exiting the sleep mode by the plurality of network switching interface devices after sleeping for a number of clock cycles specified in the unique command data packet; and G: repeating operations B, C, D, E and F.
7. The method recited in claim 6, wherein the third network and the plurality of second networks conform to the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group).
8. The method recited in claim 7, wherein the unique command data packet comprises a unique sequence of TMS (test mode select) bits causing a TAP (test access port) finite-state machine to enter a sequence not used for normal packets and bits specifying the number of clock cycles for the sleep mode.
9. The method recited in claim 7, wherein during the sleep mode, the each of the plurality of network switching interface devices is configured to prevent, a locally generated clock signal from reaching the one of the plurality of second networks, a TMS signal from reaching a TAP finite-state machine, or both.

Description

202419433 Automatic Switching Between Two Types of Interface Devices on Parallel Data Buses RELATED APPLICATIONS [01] This application claims the benefit of U.S. Provisional Patent Application No. 63/715,003, filed on November 01, 2024, and naming Jean-Francois Cote et al. as inventors, which application is incorporated entirely herein by reference. FIELD OF THE DISCLOSED TECHNOLOGY [02] The presently disclosed technology relates to the field of integrated circuit design, verification, manufacture and test. Various implementations of the disclosed technology may be particularly useful for increasing bandwidth of serial networks in a circuit. BACKGROUND OF THE DISCLOSED TECHNOLOGY [03] The increasing integration of functionality into single semiconductor devices continues to drive a significant rise in the number of functional units. These units can range from sensors (e.g., for temperature or voltage) and clock control circuitry (e.g., Phase-Locked Loops or PLLs) to scan configuration controllers or entire Built-In Self-Test (BIST) engines for memory or logic testing. Effectively operating a large number of these functional units — which includes accessing, controlling, and observing them — presents a considerable challenge to designers. [04] Traditionally, functional units are daisy-chained within a single, serial access network. This approach necessitates numerous scan operations to shift data bits into and out of these functional blocks. To reduce access time, reconfigurable scan networks can be employed as an alternative. Through specific programming operations of special elements within the access network, parts of a reconfigurable scan network can be dynamically included in or excluded from the scan path. A typical reconfigurable scan 202419433 network, conforming to IEEE 1687-2014 and IEEE 1149.1-2013, is referred to as an IJTAG network. [05] By being dynamically reconfigurable, an IJTAG network can minimize the number of shift operations required for operating desired functional units, such as configuring various aspects of a circuit's test modes. However, as device complexity and the volume of diagnostic data to be extracted increase, the inherent low speed and serial nature of the IJTAG scan network are becoming a bottleneck, leading to extended test times. [06] Attempts have been made to increase the speed of shift by introducing clock gaps around the transition of the controls (clock stretching) or by adding pipeline stages on the control signals with matching stages on the scan path. Unfortunately, those two techniques are mutually exclusive. While such solutions may help achieve shift speeds in the low 100 MHz range, the resulting bandwidth is still orders of magnitude lower than required. This limitation stems from the serial nature of these solutions and the two-edge timing employed when crossing clock domains. [07] The IEEE1687-2014 standard supports the use of multi-chain scan interfaces. However, routing many scan chains across physical block boundaries is costly, complex, and incompatible with modern core-based design flows. [08] Parallel data streaming networks have been utilized to provide fast and parallel access to a circuit’s cores (circuit blocks), significantly enhancing test data throughput. This parallel access allows cores to be accessed concurrently. For example, test data can be readily broadcast to identical cores. Parallel data streaming networks can also support infield testing, enabling efficient monitoring of a device’s state throughout its life cycle. [09] Recently, a method has been developed for utilizing parallel data streaming networks to apply IJTAG configuration data. This approach, known as high-bandwidth IJTAG (HB- IJTAG) over a parallel data streaming network (e.g., Siemens EDA's Streaming Scan Network (SSN)), significantly improves IJTAG configuration time. In this method, IJTAG can operate in two modes: a global IJTAG mode and an HB-IJTAG mode. 202419433 Although serial and inherently slow, the global IJTAG mode is necessary to initialize the HB-IJTAG mode. Conventional HB-IJTAG approaches require a fallback to the global IJTAG mode after each test pattern delivery and execution by the parallel data streaming network, but before the configuration and setup data for the next test pattern can be delivered. This necessity arises because the two types of interface devices on the parallel data streaming network — one for delivering test data to the circuit under test's cores and the other for delivering test configuration and setup data to local IJTAG networks — cannot actively listen to the network simultaneously. These two interface device types implement distinct and incompatible packet protocols. BRIEF SUMMARY OF THE DISCLOSED TECHNOLOGY [10] Various aspects of the disclosed technology relate to automatic switching between two types of interface devices, enabling continuous utilization of a data streaming network to deliver data to local serial networks